Drop per-board ram_check() calls for now.

[coreboot.git] / src / mainboard / lippert / spacerunner-lx / romstage.c

diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index 344e0eed84e3092dc259dc0b77d62e2c3ce3cd88..5f940e56617083a563d87a5670863483ec32c69a 100644 (file)
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -28,29 +28,26 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-
-#define POST_CODE(x) outb(x, 0x80)
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
 /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */
-#define SMC_CONFIG 0x01
+#if CONFIG_ONBOARD_IDE_SLAVE
+       #define SMC_CONFIG      0x03
+#else
+       #define SMC_CONFIG      0x01
+#endif
 
 #define ManualConf 1           /* No automatic strapped PLL config */
 #define PLLMSRhi 0x0000059C    /* Manual settings for the PLL */
 #define PLLMSRlo 0x00DE6001
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 static const unsigned char spdbytes[] = {      // 4x Promos V58C2512164SA-J5I
        0xFF, 0xFF,                             // only values used by Geode-LX raminit.c are set
@@ -87,7 +84,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
        if (device != DIMM0)
                return 0xFF;    /* No DIMM1, don't even try. */
 
-#if CONFIG_DEBUG
+#if CONFIG_DEBUG_SMBUS
        if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
                print_err("ERROR: spd_read_byte(DIMM0, 0x");
                print_err_hex8(address);
@@ -124,52 +121,19 @@ static int smc_send_config(unsigned char config_data)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
-       msr_t msr;
-
-       /* Setup access to the cache for under 1MB. */
-       msr.hi = 0x24fffc02;
-       msr.lo = 0x1000A000;    /* 0-A0000 write back */
-       wrmsr(CPU_RCONF_DEFAULT, msr);
-
-       msr.hi = 0x0;           /* Write back */
-       msr.lo = 0x0;
-       wrmsr(CPU_RCONF_A0_BF, msr);
-       wrmsr(CPU_RCONF_C0_DF, msr);
-       wrmsr(CPU_RCONF_E0_FF, msr);
-
-       /* Setup access to the cache for under 640K. Note MC not setup yet. */
-       msr.hi = 0x20000000;
-       msr.lo = 0xfff80;
-       wrmsr(MSR_GLIU0 + 0x20, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0x80fffe0;
-       wrmsr(MSR_GLIU0 + 0x21, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0xfff80;
-       wrmsr(MSR_GLIU1 + 0x20, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0x80fffe0;
-       wrmsr(MSR_GLIU1 + 0x21, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static const u16 sio_init_table[] = { // hi=data, lo=index
        0x0707,         // select LDN 7 (GPIO, SPI, watchdog, ...)
-       0x1E2C,         // disable ATXPowerGood
-       0x0423,         // don't delay POWerOK1/2
-       0x9072,         // watchdog triggers POWOK, counts seconds
+       0x072C,         // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal
+       0x1423,         // don't delay PoWeROK1/2
+       0x9072,         // watchdog triggers PWROK, counts seconds
 #if !CONFIG_USE_WATCHDOG_ON_BOOT
-       0x0073, 0x0074, // disable watchdog by setting timeout to 0
+       0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0
 #endif
        0xBF25, 0x172A, 0xF326, // select GPIO function for most pins
        0xFF27, 0xDF28, 0x2729, // (GP45=SUSB, GP23,22,16,15=SPI, GP13=PWROK1)
-       0x072C,         // VIN6=enabled?, FAN4/5 disabled, VIN7=internal, VIN3=internal
-       0x66B8, 0x0CB9, // enable pullups
+       0x66B8, 0x0CB9, // enable pullups on SPI, RS485_EN
        0x07C0,         // enable Simple-I/O for GP12-10= RS485_EN2,1, LIVE_LED
        0x07C8,         // config GP12-10 as output
        0x2DF5,         // map Hw Monitor Thermal Output to GP55
@@ -191,13 +155,13 @@ static void mb_gpio_init(void)
        it8712f_exit_conf();
 }
 
-void cache_as_ram_main(void)
+void main(unsigned long bist)
 {
        int err;
-       POST_CODE(0x01);
+       post_code(0x01);
 
        static const struct mem_controller memctrl[] = {
-               {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+               {.channel0 = {DIMM0, DIMM1}}
        };
 
        SystemPreInit();
@@ -214,9 +178,12 @@ void cache_as_ram_main(void)
        uart_init();
        console_init();
 
+       /* Halt if there was a built in self test failure */
+       report_bist_failure(bist);
+
        pll_reset(ManualConf);
 
-       cpuRegInit();
+       cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
        /* bit1 = on-board IDE is slave, bit0 = Spread Spectrum */
        if ((err = smc_send_config(SMC_CONFIG))) {
@@ -227,10 +194,6 @@ void cache_as_ram_main(void)
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory. */
-       /* ram_check(0, 640 * 1024); */
-
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }
-