Drop per-board ram_check() calls for now.

[coreboot.git] / src / mainboard / jetway / j7f24 / romstage.c

diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c
index 82a90dbb8a4617acc70e69c6b30f6bd84ce72884..b0c14968b962571c9c1b0daa685f8c9a4c7090ec 100644 (file)
--- a/src/mainboard/jetway/j7f24/romstage.c
+++ b/src/mainboard/jetway/j7f24/romstage.c
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-#define __PRE_RAM__
-
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -29,17 +26,15 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
 #include "northbridge/via/cn700/raminit.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/fintek/f71805f/f71805f_early_serial.c"
+#include <lib.h>
+#include <spd.h>
 
 #if CONFIG_TTYS0_BASE == 0x2f8
 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2)
@@ -47,10 +42,6 @@
 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP1)
 #endif
 
-static void memreset_setup(void)
-{
-}
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
        return smbus_read_byte(device, address);
@@ -62,7 +53,8 @@ static void enable_mainboard_devices(void)
 {
        device_t dev;
 
-       dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+       dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+                               PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
        if (dev == PCI_DEV_INVALID)
                die("Southbridge not found!!!\n");
 
@@ -91,14 +83,11 @@ static const struct mem_controller ctrl = {
        .d0f4 = 0x4000,
        .d0f7 = 0x7000,
        .d1f0 = 0x8000,
-       .channel0 = { 0x50 },
+       .channel0 = { DIMM0 },
 };
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-       unsigned long x;
-       device_t dev;
-
        /* Enable multifunction for northbridge. */
        pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 
@@ -106,25 +95,13 @@ static void main(unsigned long bist)
        uart_init();
        console_init();
 
-       print_spew("In romstage.c:main()\r\n");
-
        enable_smbus();
        smbus_fixup(&ctrl);
 
-       if (bist == 0) {
-               print_debug("doing early_mtrr\r\n");
-               early_mtrr_init();
-       }
-
        /* Halt if there was a built-in self test failure. */
        report_bist_failure(bist);
 
-       print_debug("Enabling mainboard devices\r\n");
        enable_mainboard_devices();
 
        ddr_ram_setup(&ctrl);
-
-       /* ram_check(0, 640 * 1024); */
-
-       print_spew("Leaving romstage.c:main()\r\n");
 }