Drop per-board ram_check() calls for now.

[coreboot.git] / src / mainboard / jetway / j7f24 / romstage.c

diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c
index 0e1f078f82b1f2843efc9d34343aa372a43f646f..b0c14968b962571c9c1b0daa685f8c9a4c7090ec 100644 (file)
--- a/src/mainboard/jetway/j7f24/romstage.c
+++ b/src/mainboard/jetway/j7f24/romstage.c
@@ -53,7 +53,8 @@ static void enable_mainboard_devices(void)
 {
        device_t dev;
 
-       dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+       dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+                               PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
        if (dev == PCI_DEV_INVALID)
                die("Southbridge not found!!!\n");
 
@@ -94,21 +95,13 @@ void main(unsigned long bist)
        uart_init();
        console_init();
 
-       print_spew("In romstage.c:main()\n");
-
        enable_smbus();
        smbus_fixup(&ctrl);
 
        /* Halt if there was a built-in self test failure. */
        report_bist_failure(bist);
 
-       print_debug("Enabling mainboard devices\n");
        enable_mainboard_devices();
 
        ddr_ram_setup(&ctrl);
-
-       /* ram_check(0, 640 * 1024); */
-
-       print_spew("Leaving romstage.c:main()\n");
 }
-