Remove lib/ramtest.c-include from all CAR boards.

[coreboot.git] / src / mainboard / jetway / j7f24 / romstage.c

diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c
index a0ad339cd9addd77277877377b68ed149e894fd0..1fa2f0857b72809b29f896c942cc9fc817d577e1 100644 (file)
--- a/src/mainboard/jetway/j7f24/romstage.c
+++ b/src/mainboard/jetway/j7f24/romstage.c
@@ -26,17 +26,14 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
 #include "northbridge/via/cn700/raminit.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/fintek/f71805f/f71805f_early_serial.c"
+#include <lib.h>
 
 #if CONFIG_TTYS0_BASE == 0x2f8
 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2)
@@ -44,10 +41,6 @@
 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP1)
 #endif
 
-static void memreset_setup(void)
-{
-}
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
        return smbus_read_byte(device, address);
@@ -91,11 +84,8 @@ static const struct mem_controller ctrl = {
        .channel0 = { 0x50 },
 };
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-       unsigned long x;
-       device_t dev;
-
        /* Enable multifunction for northbridge. */
        pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 
@@ -108,11 +98,6 @@ static void main(unsigned long bist)
        enable_smbus();
        smbus_fixup(&ctrl);
 
-       if (bist == 0) {
-               print_debug("doing early_mtrr\n");
-               early_mtrr_init();
-       }
-
        /* Halt if there was a built-in self test failure. */
        report_bist_failure(bist);