We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / mainboard / iwill / dk8_htx / mptable.c

diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c
index 25c02b0361e59b3876351219e4de2b58a62fb78e..8bfaec8b70b9b958e42ef37de27b4682b1e1b1dc 100644 (file)
--- a/src/mainboard/iwill/dk8_htx/mptable.c
+++ b/src/mainboard/iwill/dk8_htx/mptable.c
@@ -1,21 +1,22 @@
 #include <console/console.h>
 #include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
 #include <device/pci.h>
 #include <string.h>
 #include <stdint.h>
 #if CONFIG_LOGICAL_CPUS==1
-#include <cpu/amd/dualcore.h>
+#include <cpu/amd/multicore.h>
 #endif
 
 #include <cpu/amd/amdk8_sysconf.h>
 #include "mb_sysconf.h"
 
-extern void get_bus_conf(void);
+
 
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "IWILL   ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "DK8-HTX     ";
         struct mp_config_table *mc;
 
@@ -54,7 +55,7 @@ static void *smp_write_config_table(void *v)
         smp_write_bus(mc, m->bus_isa, "ISA   ");
 
 /*I/O APICs:   APIC ID Version State           Address*/
-       smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111
+       smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
         {
                 device_t dev;
                struct resource *res;
@@ -101,22 +102,9 @@ static void *smp_write_config_table(void *v)
                 }
 
        }
-  
-/*I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */ 
-       smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x0);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x1, m->apicid_8111, 0x1);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x0, m->apicid_8111, 0x2);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x3, m->apicid_8111, 0x3);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x4, m->apicid_8111, 0x4);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x5, m->apicid_8111, 0x5);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x6, m->apicid_8111, 0x6);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x7, m->apicid_8111, 0x7);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x8, m->apicid_8111, 0x8);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x9, m->apicid_8111, 0x9);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xc, m->apicid_8111, 0xc);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xd, m->apicid_8111, 0xd);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xe, m->apicid_8111, 0xe);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xf, m->apicid_8111, 0xf);
+
+       mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
+
 //??? What
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
 
@@ -149,14 +137,14 @@ static void *smp_write_config_table(void *v)
 
 //Slot 4 PCI-X 133/100/66
         for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26 
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26
         }
 
 //Onboard NICS
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3<<2)|0, m->apicid_8132_1, 3); //27
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4<<2)|0, m->apicid_8132_1, 0); //24
 
-//Onboard SATA 
+//Onboard SATA
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5<<2)|0, m->apicid_8132_1, 1); //25
 
         j = 0;
@@ -212,7 +200,7 @@ static void *smp_write_config_table(void *v)
        /* Compute the checksums */
        mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
        mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-       printk_debug("Wrote the mp table end at: %p - %p\n",
+       printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
                mc, smp_next_mpe_entry(mc));
        return smp_next_mpe_entry(mc);
 }