Drop per-board ram_check() calls for now.

[coreboot.git] / src / mainboard / intel / xe7501devkit / romstage.c

diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c
index 003a37f31cae9020aebfb0e2de299f2f9f796d40..e6fb83f4a69ffae4fad2b248538d769353d22e5d 100644 (file)
--- a/src/mainboard/intel/xe7501devkit/romstage.c
+++ b/src/mainboard/intel/xe7501devkit/romstage.c
@@ -6,11 +6,8 @@
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
 #include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
 #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -18,9 +15,9 @@
 #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
-#define SUPERIO_PORT   0x2e
-#define SERIAL_DEV             PNP_DEV(SUPERIO_PORT, LPC47B272_SP1)
+#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
 
 static void hard_reset(void)
 {
@@ -43,20 +40,18 @@ static void main(unsigned long bist)
                {
                        .d0 = PCI_DEV(0, 0, 0),
                        .d0f1 = PCI_DEV(0, 0, 1),
-                       .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
-                       .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
+                       .channel0 = { DIMM0, DIMM1, DIMM2, 0 },
+                       .channel1 = { DIMM4, DIMM5, DIMM6, 0 },
                },
        };
 
-       if (bist == 0) 
-       {
+       if (bist == 0) {
                // Skip this if there was a built in self test failure
                early_mtrr_init();
                enable_lapic();
        }
 
        // Get the serial port running and print a welcome banner
-
        lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
@@ -68,16 +63,15 @@ static void main(unsigned long bist)
 
        // If this is a warm boot, some initialization can be skipped
 
-       if (!bios_reset_detected()) 
+       if (!bios_reset_detected())
        {
                enable_smbus();
                // dump_spd_registers(&memctrl[0]);
                // dump_smbus_registers();
                sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
        }
-       
+
        // NOTE: ROMCC dies with an internal compiler error
        //               if the following line is removed.
        print_debug("SDRAM is up.\n");
 }
-