We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / mainboard / intel / jarrell / mptable.c

diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c
index f9d20f27873334aab736575b263655b452b33ba5..7a2a5943ff7a63602b159395b24411eaa0f05e55 100644 (file)
--- a/src/mainboard/intel/jarrell/mptable.c
+++ b/src/mainboard/intel/jarrell/mptable.c
@@ -1,13 +1,14 @@
 #include <console/console.h>
 #include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
 #include <device/pci.h>
 #include <string.h>
 #include <stdint.h>
 
-void *smp_write_config_table(void *v)
+static void *smp_write_config_table(void *v)
 {
        static const char sig[4] = "PCMP";
-       static const char oem[8] = "LNXI    ";
+       static const char oem[8] = "COREBOOT";
        static const char productid[12] = "SE7520JR20  ";
        struct mp_config_table *mc;
        unsigned char bus_num;
@@ -16,7 +17,7 @@ void *smp_write_config_table(void *v)
        unsigned char bus_pxhd_2;
        unsigned char bus_pxhd_3 = 0;
        unsigned char bus_pxhd_4 = 0;
-       unsigned char bus_pxhd_x;
+       unsigned char bus_pxhd_x = 0;
        unsigned char bus_ich5r_1;
        unsigned int bus_pxhd_id;
 
@@ -38,7 +39,7 @@ void *smp_write_config_table(void *v)
        mc->reserved = 0;
 
        smp_write_processors(mc);
-       
+
        {
                device_t dev;
 
@@ -102,7 +103,7 @@ void *smp_write_config_table(void *v)
                        }
                }
        }
-       
+
        /* define bus and isa numbers */
        for(bus_num = 0; bus_num < bus_isa; bus_num++) {
                smp_write_bus(mc, bus_num, "PCI   ");
@@ -111,7 +112,7 @@ void *smp_write_config_table(void *v)
 
        /* IOAPIC handling */
 
-       smp_write_ioapic(mc, 8, 0x20, 0xfec00000);
+       smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR);
        {
                struct resource *res;
                device_t dev;
@@ -137,6 +138,7 @@ void *smp_write_config_table(void *v)
                else {
                        printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
                }
+
                /* pxhd apic 5 */
                if(bus_pxhd_3) { /* Active riser pxhd */
                        dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,1));
@@ -165,32 +167,8 @@ void *smp_write_config_table(void *v)
                }
        }
 
-       
-       /* ISA backward compatibility interrupts  */
-       smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-               bus_isa, 0x00, 0x08, 0x00);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-               bus_isa, 0x01, 0x08, 0x01);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-               bus_isa, 0x00, 0x08, 0x02);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-               bus_isa, 0x03, 0x08, 0x03);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-               bus_isa, 0x04, 0x08, 0x04);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-               bus_isa, 0x06, 0x08, 0x06);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
-               bus_isa, 0x08, 0x08, 0x08);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-               bus_isa, 0x09, 0x08, 0x09);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-               bus_isa, 0x0c, 0x08, 0x0c);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-               bus_isa, 0x0d, 0x08, 0x0d);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-               bus_isa, 0x0e, 0x08, 0x0e);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
-               bus_isa, 0x0f, 0x08, 0x0f);
+       mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
+
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
                bus_isa, 0x0a, 0x08, 0x10);
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
@@ -218,8 +196,8 @@ void *smp_write_config_table(void *v)
        smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
                bus_isa, 0x00, MP_APIC_ALL, 0x01);
 
+       /* FIXME verify I have the irqs handled for all of the risers */
 
-#warning "FIXME verify I have the irqs handled for all of the risers"
        /* 2:3.0 PCI Slot 1 */
        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
                bus_pxhd_1, (3<<2)|0, 0x9, 0x0);