Remove lib/ramtest.c-include from all CAR boards.

[coreboot.git] / src / mainboard / intel / eagleheights / romstage.c

diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 75c4d7375c8ace5646fb8dc7e6d32a9121e0769e..fe981d6c0a48dc9f0328c167498979330b77d8a6 100644 (file)
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -20,8 +20,6 @@
  * MA 02110-1301 USA
  */
 
-#define __PRE_RAM__
-
 #include <delay.h>
 
 #include <stdint.h>
@@ -31,14 +29,11 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
 
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "reset.c"
@@ -63,9 +58,6 @@
 #define UART_MSR 0x06
 #define UART_SCR 0x07
 
-#define SIO_GPIO_BASE 0x680
-#define SIO_XBUS_BASE 0x4880
-
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
@@ -104,10 +96,6 @@
 #define RCBA_FD    0x3418 /* 32 bit */
 #define RCBA_PRC   0x341C /* 32 bit */
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-       /* nothing to do */
-}
 static inline int spd_read_byte(u16 device, u8 address)
 {
        return smbus_read_byte(device, address);
@@ -121,8 +109,8 @@ static inline int spd_read_byte(u16 device, u8 address)
 #include "northbridge/intel/i3100/reset_test.c"
 #include "debug.c"
 
-void early_config(void) {
-       device_t dev;
+static void early_config(void)
+{
        u32 gcs, rpc, fd;
 
        /* Enable RCBA */
@@ -165,7 +153,7 @@ void early_config(void) {
        pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
 }
 
-void real_main(unsigned long bist)
+void main(unsigned long bist)
 {
        /* int boot_mode = 0; */
 
@@ -234,5 +222,3 @@ void real_main(unsigned long bist)
        sdram_initialize(ARRAY_SIZE(mch), mch);
 }
 
-/* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */
-#include "cpu/intel/model_6ex/cache_as_ram_disable.c"