We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / mainboard / intel / eagleheights / mptable.c

diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index d2ff79870bf564a565bf9f13960be6347726ba77..33d7b014807813840a7dc05ff4a6d6aa8d0b9607 100644 (file)
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -23,6 +23,7 @@
 
 #include <console/console.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <arch/smp/mpspec.h>
 #include <device/pci.h>
 #include <string.h>
@@ -61,7 +62,7 @@
 static void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
-        static const char oem[8] = "Intel   ";
+        static const char oem[8] = "COREBOOT";
         static const char productid[12] = "EagleHeights";
         struct mp_config_table *mc;
        unsigned char bus_num, bus_chipset, bus_isa, bus_pci;
@@ -144,7 +145,7 @@ static void *smp_write_config_table(void *v)
        smp_write_bus(mc, bus_isa, "ISA   ");
 
        /*I/O APICs: APIC ID Version State Address*/
-       smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+       smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
        /*
        {
                device_t dev;
@@ -179,39 +180,7 @@ static void *smp_write_config_table(void *v)
                 }
        }
        */
-       /*I/O Ints:     Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
-       /* IRQ0 8254 Counter 0, MNT0 */
-       smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  0, IO_APIC0,  0);
-       /* IRQ1 Keyboard */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  1, IO_APIC0,  1);
-       /* IRQ2 8259 cascade only */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  0, IO_APIC0,  2);
-       /* IRQ3 COM2, Option for PIRQx */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  3, IO_APIC0,  3);
-       /* IRQ4 COM1, Option for PIRQx */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  4, IO_APIC0,  4);
-       /* IRQ5 Option for PIRQx */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  5, IO_APIC0,  5);
-       /* IRQ6 Option for PIRQx */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  6, IO_APIC0,  6);
-       /* IRQ7 OPtion for PIRQx */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  7, IO_APIC0,  7);
-       /* IRQ8# RTC, MNT1 */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_EDGE   |MP_IRQ_POLARITY_HIGH,    bus_isa,  8, IO_APIC0,  8);
-       /* IRQ9 Option for PIRQx, SCI, TCO */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa,  9, IO_APIC0,  9);
-       /* IRQ10 Option for PIRQx, SCI, TCO */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 10);
-       /* IRQ11 Option for PIRQx, SCI, TCO, MMT2 */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 11);
-       /* IRQ12 Mouse, Option for PIRQx */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 12);
-       /* IRQ13 Floating point interrupt generated off of the processor assertion of FERR# */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 13, IO_APIC0, 13);
-       /* IRQ14 PIRQx Sata primary (legacy mode) */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 14, IO_APIC0, 14);
-       /* IRQ15 PIRQx Sata secondary (legacy mode) */
-       smp_write_intsrc(mc, mp_INT,    MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 15, IO_APIC0, 15);
+       mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0);
 
        /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
        smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0);