Remove various .c #includes from Intel i810/i82801ax/i82801bx boards.
[coreboot.git] / src / mainboard / intel / d810e2cb / romstage.c
index 34371f5834f00046b43ee749bcf3bc0cb2a55693..fcdbb3156e513d99f1d445a9d08eeabf1ec552c5 100644 (file)
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82801bx/i82801bx.h"
-#include "southbridge/intel/i82801bx/i82801bx_early_smbus.c"
 #include "northbridge/intel/i82810/raminit.h"
-#include "lib/debug.c"
 #include "pc80/udelay_io.c"
-#include "lib/delay.c"
 #include "cpu/x86/bist.h"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "gpio.c"
 
 #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
-{
-       return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i82810/raminit.c"
-/* #include "northbridge/intel/i82810/debug.c" */
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
 
 void main(unsigned long bist)
 {
-       /* Set southbridge and superio gpios */
+       /* Set southbridge and Super I/O GPIOs. */
        mb_gpio_init();
 
        smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -58,10 +49,8 @@ void main(unsigned long bist)
 
        report_bist_failure(bist);
        enable_smbus();
-       /* dump_spd_registers(); */
+       dump_spd_registers();
        sdram_set_registers();
        sdram_set_spd_registers();
        sdram_enable();
-       /* ram_check(0, 640 * 1024); */
 }
-