*/
#include <stdint.h>
+#include <stdlib.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
+#include <spd.h>
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
static inline int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
/* Hold Count - how long we will sit in reset */
#define PLLMSRlo 0x00DE6000
-#define DIMM0 0xA0
-#define DIMM1 0xA2
-
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
+#include "cpu/amd/model_lx/msrinit.c"
-static void msr_init(void)
-{
- msr_t msr;
-
- /* Setup access to the cache for under 1MB. */
- msr.hi = 0x24fffc02;
- msr.lo = 0x1000A000; /* 0-A0000 write back */
- wrmsr(CPU_RCONF_DEFAULT, msr);
-
- msr.hi = 0x0; /* Write back */
- msr.lo = 0x0;
- wrmsr(CPU_RCONF_A0_BF, msr);
- wrmsr(CPU_RCONF_C0_DF, msr);
- wrmsr(CPU_RCONF_E0_FF, msr);
-
- /* Setup access to the cache for under 640K. Note MC not setup yet. */
- msr.hi = 0x20000000;
- msr.lo = 0xfff80;
- wrmsr(MSR_GLIU0 + 0x20, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0x80fffe0;
- wrmsr(MSR_GLIU0 + 0x21, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0xfff80;
- wrmsr(MSR_GLIU1 + 0x20, msr);
-
- msr.hi = 0x20000000;
- msr.lo = 0x80fffe0;
- wrmsr(MSR_GLIU1 + 0x21, msr);
-}
-
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup. */
-}
-
-void cache_as_ram_main(void)
+void main(unsigned long bist)
{
post_code(0x01);
static const struct mem_controller memctrl[] = {
- {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+ {.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
* early MSR setup for CS5536.
*/
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- mb_gpio_init();
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
pll_reset(ManualConf);
- cpuRegInit();
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
- /* ram_check(0, 640 * 1024); */
-
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
-