* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value

[coreboot.git] / src / mainboard / ibase / mb899 / romstage.c

diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 53750dfc080a2ff1efb8204b8b7daba22c27ddbe..5cd1fe571c337eae63090d959d33b3d40634c7cb 100644 (file)
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -26,29 +26,21 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
-
+#include <lib.h>
 #include "superio/winbond/w83627ehg/w83627ehg.h"
-
 #include <pc80/mc146818rtc.h>
-
 #include <console/console.h>
+#include <usbdebug.h>
 #include <cpu/x86/bist.h>
-
-#if CONFIG_USBDEBUG
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
-#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-
-#include "northbridge/intel/i945/udelay.c"
+#include "superio/winbond/w83627ehg/early_serial.c"
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
 
 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
+#define DUMMY_DEV PNP_DEV(0x4e, 0)
 
-#include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+void setup_ich7_gpios(void)
 {
        printk(BIOS_DEBUG, " GPIOS...");
        /* General Registers */
@@ -64,18 +56,6 @@ static void setup_ich7_gpios(void)
        outl(0x00010035, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-       return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
        // Enable Serial IRQ
@@ -98,7 +78,7 @@ static void early_superio_config_w83627ehg(void)
 {
        device_t dev;
 
-       dev=PNP_DEV(0x4e, W83627EHG_SP1);
+       dev = DUMMY_DEV;
        pnp_enter_ext_func_mode(dev);
 
        pnp_write_config(dev, 0x24, 0xc4); // PNPCSV
@@ -245,22 +225,13 @@ static void early_ich7_init(void)
 
 #include <cbmem.h>
 
-// Now, this needs to be included because it relies on the symbol
-// __PRE_RAM__ being set during CAR stage (in order to compile the
-// BSS free versions of the functions). Either rewrite the code
-// to be always BSS free, or invent a flag that's better suited than
-// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
-//
-#include "lib/cbmem.c"
-
 void main(unsigned long bist)
 {
        u32 reg32;
        int boot_mode = 0;
 
-       if (bist == 0) {
+       if (bist == 0)
                enable_lapic();
-       }
 
        ich7_enable_lpc();
        early_superio_config_w83627ehg();
@@ -268,11 +239,6 @@ void main(unsigned long bist)
        /* Set up the console */
        uart_init();
 
-#if CONFIG_USBDEBUG
-       i82801gx_enable_usbdebug(1);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */
@@ -312,7 +278,7 @@ void main(unsigned long bist)
        dump_spd_registers();
 #endif
 
-       sdram_initialize(boot_mode);
+       sdram_initialize(boot_mode, NULL);
 
        /* Perform some initialization that must run before stage2 */
        early_ich7_init();
@@ -372,4 +338,3 @@ void main(unsigned long bist)
        }
 #endif
 }
-