This patch unifies the use of config options in v2 to all start with CONFIG_

[coreboot.git] / src / mainboard / hp / dl145_g3 / Config.lb

diff --git a/src/mainboard/hp/dl145_g3/Config.lb b/src/mainboard/hp/dl145_g3/Config.lb
index 1095cde182dab3b236fbc909571404fb52ff83d1..12ea977babff980a7f54d1165f079d14ac1a0cf9 100644 (file)
--- a/src/mainboard/hp/dl145_g3/Config.lb
+++ b/src/mainboard/hp/dl145_g3/Config.lb
@@ -25,6 +25,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
 include /config/nofailovercalculation.lb
 
 arch i386 end
@@ -38,18 +40,18 @@ driver mainboard.o
 #needed by irq_tables and mptable and acpi_tables
 object get_bus_conf.o
 
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
 
 if CONFIG_USE_INIT
        makerule ./auto.o
-               depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-               action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+               depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+               action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
        end
 else
        makerule ./auto.inc
-               depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-               action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+               depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+               action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
                action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
                action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
        end
@@ -58,7 +60,7 @@ end
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
        mainboardinit cpu/x86/16bit/entry16.inc
        ldscript /cpu/x86/16bit/entry16.lds
 end
@@ -76,7 +78,7 @@ mainboardinit cpu/x86/32bit/entry32.inc
 ##
 ## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
        mainboardinit cpu/x86/16bit/reset16.inc
        ldscript /cpu/x86/16bit/reset16.lds
 else
@@ -100,7 +102,7 @@ ldscript /arch/i386/lib/id.lds
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
                ldscript /arch/i386/lib/failover.lds
 end
 
@@ -192,15 +194,8 @@ chip northbridge/amd/amdk8/root_complex
                                        device pci 2.0 on end # USB     0x0223
                                        device pci 2.1 on end # USB
                                        device pci 2.2 on end # USB
-                                       chip drivers/pci/onboard
-                                               # it is in bcm5785_0 bus, but the device id can
-                                               # not be changed even unitid is changed, fake one
-                                               # to get the rom_address
-                                               # if HT_CHAIN_END_UNITID_BASE=0, it is 4,
-                                               # if HT_CHAIN_END_UNITID_BASE=1, it is 3
-                                               device pci 4.0 on end
-                                               register "rom_address" = "0xfff00000"
-                                       end
+                                       device pci 3.0 on end # VGA
+                                       
                                        #bx_a013+ start
                                        #chip drivers/pci/onboard    #SATA2
                                        #       device pci 5.0 on end