Drop per-board ram_check() calls for now.

[coreboot.git] / src / mainboard / gigabyte / ma78gm / romstage.c

diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 9225e2616e7b8eaabacf7359190205e64169fe49..21f80c25672a859a841a873777d205fc4b82e366 100644 (file)
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -21,21 +21,10 @@
 #define SYSTEM_TYPE 1  /* DESKTOP */
 //#define SYSTEM_TYPE 2        /* MOBILE */
 
-#define RAMINIT_SYSINFO 1
-
-#define SET_NB_CFG_54 1
-
-//used by raminit
-#define QRANK_DIMM_SUPPORT 1
-
 //used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0
 
-//used by init_cpus and fidvid
-#define SET_FIDVID 1
-#define SET_FIDVID_CORE_RANGE 0
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -49,73 +38,45 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
-
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-
 static int smbus_read_byte(u32 device, u32 address);
-
 #include "superio/ite/it8718f/it8718f_early_serial.c"
-
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
-
+#include <usbdebug.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-
 #include "southbridge/amd/rs780/rs780_early_setup.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static int spd_read_byte(u32 device, u32 address)
 {
-       int result;
-       result = smbus_read_byte(device, address);
-       return result;
+       return smbus_read_byte(device, address);
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
-
-
-#define RC00  0
-#define RC01  1
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
+#include <spd.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-
        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
        static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
-       u32 bsp_apicid = 0;
-       u32 val;
+       u32 bsp_apicid = 0, val;
        msr_t msr;
 
        if (!cpu_init_detectedx && boot_cpu()) {
@@ -124,7 +85,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                /* mov bsp to bus 0xff when > 8 nodes */
                set_bsp_node_CHtExtNodeCfgEn();
                enumerate_ht_chain();
-
                sb700_pci_port80();
        }
 
@@ -152,7 +112,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        console_init();
        printk(BIOS_DEBUG, "\n");
 
-
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
 
@@ -190,13 +149,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         */
        wait_all_core0_started();
 
- #if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS==1
        /* Core0 on each node is configured. Now setup any additional cores. */
        printk(BIOS_DEBUG, "start_other_cores()\n");
        start_other_cores();
        post_code(0x37);
        wait_all_other_cores_started(bsp_apicid);
- #endif
+#endif
 
        post_code(0x38);
 
@@ -204,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        rs780_early_setup();
        sb700_early_setup();
 
- #if SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 
@@ -225,7 +184,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        /* show final fid and vid */
        msr=rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
- #endif
+#endif
 
        rs780_htinit();
 
@@ -257,9 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
 */
 
-//     ram_check(0x00200000, 0x00200000 + (640 * 1024));
-//     ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
 //     die("After MCT init before CAR disabled.");
 
        rs780_before_pci_init();
@@ -270,4 +226,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        post_cache_as_ram();    // BSP switch stack to ram, copy then execute LB.
        post_code(0x43);        // Should never see this post code.
 }
-