## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
+include /config/failovercalculation.lb
arch i386 end
#needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./cache_as_ram_auto.inc
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
- action "perl -e 's/.rodata/.rom.data/g' -pi $@"
- action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
+ action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
+ action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
-end
-
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
makerule ./apc_auto.o
- depends "$(MAINBOARD)/apc_auto.c option_table.h"
- action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+ depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
end
ldscript /arch/i386/init/ldscript_apc.lb
end
##
## Build our 16 bit and 32 bit coreboot entry code
##
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
-
##
## Build our reset vector (This is where coreboot is entered)
##
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
ldscript /cpu/x86/32bit/reset32.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
##
## ROMSTRAP table for MCP55
##
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
mainboardinit southbridge/nvidia/mcp55/romstrap.inc
ldscript /southbridge/nvidia/mcp55/romstrap.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
mainboardinit southbridge/nvidia/mcp55/romstrap.inc
ldscript /southbridge/nvidia/mcp55/romstrap.lds
end
end
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
- if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
+ if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
- end
end
end
+if CONFIG_HAVE_FANCTL
+ object fanctl.o
+end
+
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
+
+##
+## ACPI Support
+##
+if CONFIG_HAVE_ACPI_TABLES
+ object acpi_tables.o
+ makerule dsdt.c
+ depends "$(CONFIG_MAINBOARD)/dsdt.asl"
+ action "iasl -p $(PWD)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
+ action "mv dsdt.hex dsdt.c"
+ end
+ object ./dsdt.o
end
##
## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
+config chip.h
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
projects / coreboot.git / blobdiff