Drop CONFIG_CHIP_NAME. Those config statements in Config.lb should

[coreboot.git] / src / mainboard / gigabyte / ga_2761gxdk / Config.lb

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
index c7b12507e4678369680e20c865f01dcaa3af554e..73f4d6e5fb6c506753aa3ca69835b52968ea541c 100644 (file)
--- a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
@@ -1,5 +1,5 @@
 ##
-## This file is part of the LinuxBIOS project.
+## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2007 AMD
 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
@@ -23,7 +23,7 @@
 
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FAILOVER_IMAGE
        default ROM_SECTION_SIZE   = FAILOVER_SIZE
@@ -40,18 +40,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -87,14 +87,14 @@ if USE_DCACHE_RAM
        if CONFIG_USE_INIT
                makerule ./cache_as_ram_auto.o
                        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+                       action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
                end
        else
                makerule ./cache_as_ram_auto.inc
                        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(CPU_OPT) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
-                       action "perl -e 's/.rodata/.rom.data/g' -pi $@"
-                       action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+                       action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(CPU_OPT) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin $(DEBUG_CFLAGS) -Wall -c -S -o $@"
+                       action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
+                       action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
                end
        end
 
@@ -113,7 +113,7 @@ end
 
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE
@@ -141,7 +141,7 @@ end
 
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE
@@ -190,7 +190,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
@@ -223,9 +223,7 @@ end
 ##
 ## Include the secondary Configuration files
 ##
-if CONFIG_CHIP_NAME
-       config chip.h
-end
+config chip.h
 
 chip northbridge/amd/amdk8/root_complex
         device apic_cluster 0 on