#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
-#include <usbdebug.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include "northbridge/intel/i945/i945.h"
#include "northbridge/intel/i945/raminit.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
+#include "option_table.h"
void setup_ich7_gpios(void)
{
static void ich7_enable_lpc(void)
{
+ int lpt_en = 0;
+ if (read_option(lpt, 0) != 0) {
+ lpt_en = 1<<2; // enable LPT
+ }
// Enable Serial IRQ
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
// decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
// decode range
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
// Enable 0x02e0 - 0x2ff
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1);
// Enable 0x600 - 0x6ff
#include <cbmem.h>
-// Now, this needs to be included because it relies on the symbol
-// __PRE_RAM_ being set during CAR stage (in order to compile the
-// BSS free versions of the functions). Either rewrite the code
-// to be always BSS free, or invent a flag that's better suited than
-// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
-//
-#include "lib/cbmem.c"
-
void main(unsigned long bist)
{
u32 reg32;
early_superio_config();
/* Set up the console */
- uart_init();
-
-#if CONFIG_USBDEBUG
- i82801gx_enable_usbdebug(1);
- early_usbdebug_init();
-#endif
console_init();
/* Halt if there was a built in self test failure */
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
/* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
}
#endif
}