This patch unifies the use of config options in v2 to all start with CONFIG_

[coreboot.git] / src / mainboard / eaglelion / 5bcm / auto.c

diff --git a/src/mainboard/eaglelion/5bcm/auto.c b/src/mainboard/eaglelion/5bcm/auto.c
index cefa559ffe73bd0a94d1a857b5ff6d379735881d..096cebe2f78f91736ece2471c4fda78d751238db 100644 (file)
--- a/src/mainboard/eaglelion/5bcm/auto.c
+++ b/src/mainboard/eaglelion/5bcm/auto.c
@@ -6,24 +6,24 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
+#include <stdlib.h>
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 //#include "southbridge/intel/i440bx/i440bx_early_smbus.c"
-#include "superio/NSC/pc97317/pc97317_early_serial.c"
+#include "superio/nsc/pc97317/pc97317_early_serial.c"
 //#include "northbridge/intel/i440bx/raminit.h"
 #include "cpu/x86/bist.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
 
-//#include "debug.c"
 //#include "lib/delay.c"
 
 #include "northbridge/amd/gx1/raminit.c"
 
 static void main(unsigned long bist)
 {
-       pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE);
+       pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
 
@@ -48,7 +48,7 @@ static void main(unsigned long bist)
 #endif
        };
        int i;
-       for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
+       for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
                ram_check(check_addrs[i].lo, check_addrs[i].hi);
        }
 #endif