Drop per-board ram_check() calls for now.

[coreboot.git] / src / mainboard / digitallogic / adl855pc / romstage.c

diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c
index 2e1a96c91b858c5b4cb7f9a600b95e706bb54e36..823e5effa4b3a6e50b16fcc63031478747eed30b 100644 (file)
--- a/src/mainboard/digitallogic/adl855pc/romstage.c
+++ b/src/mainboard/digitallogic/adl855pc/romstage.c
@@ -3,51 +3,23 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
-#if 0
-#include <arch/smp/lapic.h>
-#endif
 #include <arch/hlt.h>
-//#include "option_table.h"
 #include <stdlib.h>
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <lib.h>
+#include "pc80/udelay_io.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
 #include "southbridge/intel/i82801dx/i82801dx.h"
 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"
-
-#if 0
-#include "cpu/p6/apic_timer.c"
-#include "lib/delay.c"
-#endif
-
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/intel/i855/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c" 
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static void hard_reset(void)
-{
-        outb(0x0e, 0x0cf9);
-}
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-        /* nothing to do */
-}
- 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
        return smbus_read_byte(device, address);
@@ -55,27 +27,16 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "northbridge/intel/i855/raminit.c"
 #include "northbridge/intel/i855/reset_test.c"
-#include "lib/generic_sdram.c"
 
-
-#include "cpu/intel/model_6bx/cache_as_ram_disable.c"
-
-void real_main(unsigned long bist)
+void main(unsigned long bist)
 {
-       static const struct mem_controller memctrl[] = {
-               {
-                       .d0 = PCI_DEV(0, 0, 1),
-                       .channel0 = { (0xa<<3)|0, 0 },
-               },
-       };
-
        if (bist == 0) {
 #if 0
                enable_lapic();
                init_timer();
 #endif
        }
-        
+
         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
@@ -87,28 +48,19 @@ void real_main(unsigned long bist)
        print_pci_devices();
 #endif
 
-       if(!bios_reset_detected()) {
+       if (!bios_reset_detected()) {
                enable_smbus();
 #if 0
-               dump_spd_registers(&memctrl[0]);
+               dump_spd_registers();
                dump_smbus_registers();
 #endif
-               memreset_setup();
-
-               sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
-
-       } 
+               sdram_set_registers();
+               sdram_set_spd_registers();
+               sdram_enable();
+       }
 
 #if 0
        dump_pci_devices();
        dump_pci_device(PCI_DEV(0, 0, 0));
-
-       // Check all of memory
-       ram_check(0x00000000, msr.lo+(msr.hi<<32));
-       // Check 16MB of memory @ 0
-       ram_check(0x00000000, 0x01000000);
-       // Check 16MB of memory @ 2GB 
-       ram_check(0x80000000, 0x81000000);
 #endif
 }
-