/*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
*
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
*
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include <stdlib.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
-#include "mainboard/asus/mew-vm/debug.c" /* FIXME */
+#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-#include "sdram/generic_sdram.c"
static void main(unsigned long bist)
{
- static const struct mem_controller memctrl[] = {
- {
- .d0 = PCI_DEV(0, 0, 0),
- .channel0 = {0x50, 0x51, 0x52, 0x53},
- }
- };
-
if (bist == 0)
early_mtrr_init();
/* FIXME: Should be PC97307! */
- pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
report_bist_failure(bist);
enable_smbus();
- /* dump_spd_registers(&memctrl[0]); */
- sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl);
+ /* dump_spd_registers(); */
+ sdram_set_registers();
+ sdram_set_spd_registers();
+ sdram_enable();
/* ram_check(0, 640 * 1024); */
}