Drop CONFIG_CHIP_NAME. Those config statements in Config.lb should

[coreboot.git] / src / mainboard / broadcom / blast / Config.lb

diff --git a/src/mainboard/broadcom/blast/Config.lb b/src/mainboard/broadcom/blast/Config.lb
index 412afb4b7d3efcf0536d95a3250aa9a13b825c4f..d77d099f4af0c4eae96264747c21e316ee8d477a 100644 (file)
--- a/src/mainboard/broadcom/blast/Config.lb
+++ b/src/mainboard/broadcom/blast/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
        default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
-default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -56,23 +56,23 @@ if USE_DCACHE_RAM
 
                makerule ./cache_as_ram_auto.o
                        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" 
+                       action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" 
                end
 
        else    
                 
                makerule ./cache_as_ram_auto.inc
                        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"         
-                       action "perl -e 's/.rodata/.rom.data/g' -pi $@"
-                       action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+                       action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"         
+                       action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
+                       action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
                end
 
        end
 
 end
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -88,7 +88,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
        mainboardinit cpu/x86/16bit/reset16.inc 
@@ -112,7 +112,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
@@ -145,9 +145,7 @@ end
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-       config chip.h
-end
+config chip.h
 
 # sample config for broadcom/blast 
 chip northbridge/amd/amdk8/root_complex
@@ -217,7 +215,7 @@ chip northbridge/amd/amdk8/root_complex
                                        end
                                         device pci 1.1 on end # IDE        0x0214
                                         device pci 1.2 on     # LPC        0x0234
-                                                chip superio/NSC/pc87417
+                                                chip superio/nsc/pc87417
                                                         device  pnp 2e.0 off  # Floppy
                                                                  io 0x60 = 0x3f0
                                                                 irq 0x70 = 6