/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <stdlib.h>
-#include "pc80/serial.c"
-#include "console/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
#include "northbridge/intel/i82810/raminit.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
+#include "southbridge/intel/i82801ax/i82801ax.h"
+#include "pc80/udelay_io.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
-#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
-#include "lib/debug.c"
-#include "pc80/udelay_io.c"
-#include "lib/delay.c"
-#include "northbridge/intel/i82810/raminit.c"
-#include "northbridge/intel/i82810/debug.c"
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
enable_smbus();
-
- /* Halt if there was a built in self test failure. */
report_bist_failure(bist);
-
- /* dump_spd_registers(); */
-
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
-
- /* Check RAM. */
- /* ram_check(0, 640 * 1024); */
}
-