run uart_init() from console_init, just like the other console initialization functions.

[coreboot.git] / src / mainboard / asus / a8v-e_se / romstage.c

diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index b8a4483affdd4b97df3466c365c795f2bc96810f..4e08859746e70803c768696f539ddb0b3ca3a834 100644 (file)
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -5,7 +5,7 @@
  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
  * Copyright (C) 2006 MSI
  * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> 
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,21 +22,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define RAMINIT_SYSINFO 1
-
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
 unsigned int get_sbdn(unsigned bus);
 
-/* Used by raminit. */
-#define QRANK_DIMM_SUPPORT 1
-
-/* Used by init_cpus and fidvid */
-#define SET_FIDVID 1
-
-/* If we want to wait for core1 done before DQS training, set it to 0. */
-#define SET_FIDVID_CORE0_ONLY 1
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -44,10 +31,8 @@ unsigned int get_sbdn(unsigned bus);
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
@@ -55,32 +40,28 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
-#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
-#include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
+#include "superio/winbond/w83627ehg/early_serial.c"
+#include "southbridge/via/vt8237r/early_smbus.c"
+#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
+#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
 #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
 
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
        return smbus_read_byte(device, address);
 }
 
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
-static void soft_reset(void)
+#include <reset.h>
+void soft_reset(void)
 {
        uint8_t tmp;
 
@@ -98,17 +79,13 @@ static void soft_reset(void)
        }
 }
 
-#define K8_4RANK_DIMM_SUPPORT 1
-
+#include "southbridge/via/k8t890/early_car.c"
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-#include "southbridge/via/k8t890/k8t890_early_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
@@ -169,20 +146,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
                // Node 0
-               (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
-               (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
+               DIMM0, DIMM2, 0, 0,
+               DIMM1, DIMM3, 0, 0,
                // Node 1
-               (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
-               (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
+               DIMM4, DIMM6, 0, 0,
+               DIMM5, DIMM7, 0, 0,
        };
        unsigned bsp_apicid = 0;
        int needs_reset = 0;
-       struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE 
+       struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
                + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
        sio_init();
        w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-       uart_init();
        console_init();
        enable_rom_decode();
 
@@ -195,11 +171,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
                enumerate_ht_chain();
        }
 
+       // FIXME why is this executed again? --->
        sio_init();
        w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-       uart_init();
        console_init();
        enable_rom_decode();
+       // <--- FIXME why is this executed again?
 
        print_info("now booting... real_main\n");
 
@@ -246,4 +223,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
        post_cache_as_ram();
 }
-