Drop CONFIG_CHIP_NAME. Those config statements in Config.lb should

[coreboot.git] / src / mainboard / amd / serengeti_cheetah / Config.lb

diff --git a/src/mainboard/amd/serengeti_cheetah/Config.lb b/src/mainboard/amd/serengeti_cheetah/Config.lb
index f395e4138de552207c1da5afc3269436e0cd15b9..039bf4bb05938691e461d177e55fb40961627cf7 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah/Config.lb
+++ b/src/mainboard/amd/serengeti_cheetah/Config.lb
@@ -1,6 +1,6 @@
 ##
 ## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 if USE_FAILOVER_IMAGE
        default ROM_SECTION_SIZE   = FAILOVER_SIZE
@@ -17,18 +17,18 @@ end
 
 ##
 ## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
 ##
-default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -90,7 +90,7 @@ if HAVE_ACPI_TABLES
         object fadt.o
        makerule dsdt.c
                depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
-               action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
+               action  "iasl -p $(PWD)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
                action  "mv dsdt_lb.hex dsdt.c"
        end
         object ./dsdt.o
@@ -100,11 +100,25 @@ if HAVE_ACPI_TABLES
         if ACPI_SSDTX_NUM
             makerule ssdt2.c
                         depends "$(MAINBOARD)/dx/pci2.asl"
-                        action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl"
+                        action  "iasl -p $(PWD)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
                         action  "mv pci2.hex ssdt2.c"
             end
             object ./ssdt2.o
+            makerule ssdt3.c
+                        depends "$(MAINBOARD)/dx/pci3.asl"
+                        action  "iasl -p $(PWD)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
+                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
+                        action  "mv pci3.hex ssdt3.c"
+            end
+            object ./ssdt3.o
+            makerule ssdt4.c
+                        depends "$(MAINBOARD)/dx/pci4.asl"
+                        action  "iasl -p $(PWD)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
+                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
+                        action  "mv pci4.hex ssdt4.c"
+            end
+            object ./ssdt4.o
         end
 end
 
@@ -114,18 +128,17 @@ if USE_DCACHE_RAM
                # compile cache_as_ram.c to auto.o
                makerule ./cache_as_ram_auto.o
                        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" 
+                       action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" 
                end
 
        else   
                #compile cache_as_ram.c to auto.inc 
                makerule ./cache_as_ram_auto.inc
                        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-                       action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"         
-                       action "perl -e 's/.rodata/.rom.data/g' -pi $@"
-                       action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+                       action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"         
+                       action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
+                       action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
                end
-
        end
 end
 
@@ -134,14 +147,14 @@ else
     if CONFIG_AP_CODE_IN_CAR
        makerule ./apc_auto.o
                depends "$(MAINBOARD)/apc_auto.c option_table.h"
-               action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+               action "$(CC) -I$(TOP)/src -I. $(DISTRO_CFLAGS) $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
        end
        ldscript /arch/i386/init/ldscript_apc.lb
     end
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 
 if HAVE_FAILOVER_BOOT
@@ -168,7 +181,7 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if HAVE_FAILOVER_BOOT
     if USE_FAILOVER_IMAGE 
@@ -202,7 +215,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
@@ -240,9 +253,7 @@ end
 ##
 ## Include the secondary Configuration files 
 ##
-if CONFIG_CHIP_NAME
-       config chip.h
-end
+config chip.h
 
 # sample config for amd/serengeti_cheetah 
 chip northbridge/amd/amdk8/root_complex