Re-integrate "USE_OPTION_TABLE" code.

[coreboot.git] / src / mainboard / amd / pistachio / romstage.c

diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 0db2f3413b1ac6d0ab209d04016d750e1667eaeb..182fab8a0b958c12d18bc92b6d9475e5b41a38d1 100644 (file)
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -17,11 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-#define __PRE_RAM__
-
 #define RAMINIT_SYSINFO 1
-#define K8_SET_FIDVID 1
+#define SET_FIDVID 1
 #define QRANK_DIMM_SUPPORT 1
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
@@ -37,12 +34,8 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-
-#define post_code(x) outb(x, 0x80)
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
@@ -53,7 +46,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -62,7 +55,7 @@
 #include "southbridge/amd/sb600/sb600_early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
 
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
+/* CAN'T BE REMOVED! memory bus reset hook for some broken amd k8 boards. */
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -87,7 +80,7 @@ static inline int spd_read_byte(u32 device, u32 address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#include "cpu/amd/car/copy_and_run.c"
+
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
@@ -107,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
            (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
                                CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
-       if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+       if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */
                enumerate_ht_chain();
@@ -132,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
-       printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
+       printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 
        setup_pistachio_resource_map();
 
@@ -162,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
                /* Read FIDVID_STATUS */
                msr=rdmsr(0xc0010042);
-               printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+               printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
                enable_fid_change();
                enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -170,10 +163,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
                /* show final fid and vid */
                msr=rdmsr(0xc0010042);
-               printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
+               printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 
        } else {
-               printk_debug("Changing FIDVID not supported\n");
+               printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
        }
 
        post_code(0x05);
@@ -181,19 +174,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        needs_reset = optimize_link_coherent_ht();
        needs_reset |= optimize_link_incoherent_ht(sysinfo);
        rs690_htinit();
-       printk_debug("needs_reset=0x%x\n", needs_reset);
+       printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 
        post_code(0x06);
 
        if (needs_reset) {
-               print_info("ht reset -\r\n");
+               print_info("ht reset -\n");
                soft_reset();
        }
 
        allow_all_aps_stop(bsp_apicid);
 
        /* It's the time to set ctrl now; */
-       printk_debug("sysinfo->nodes: %2x  sysinfo->ctrl: %2x  spd_addr: %2x\n",
+       printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
                     sysinfo->nodes, sysinfo->ctrl, spd_addr);
        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
@@ -208,3 +201,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_cache_as_ram();
 }
+