Drop per-board ram_check() calls for now.

[coreboot.git] / src / mainboard / amd / norwich / romstage.c

diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index 19c5b17ade4eb9b96ba6a8586027d5ab46fce3b7..f60313842aa03e1d3fa0d740b86c0de8cf4b0f4e 100644 (file)
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -18,24 +18,19 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
 #include <stdint.h>
+#include <stdlib.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
-
-#define POST_CODE(x) outb(x, 0x80)
-
+#include <spd.h>
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
@@ -47,8 +42,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #define ManualConf 0           /* Do automatic strapped PLL config */
 #define PLLMSRhi 0x00001490    /* manual settings for the PLL */
 #define PLLMSRlo 0x02000030
-#define DIMM0 0xA0
-#define DIMM1 0xA2
 
 #include "northbridge/amd/lx/raminit.h"
 #include "northbridge/amd/lx/pll_reset.c"
@@ -56,51 +49,14 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
+#include "cpu/amd/model_lx/msrinit.c"
 
-static void msr_init(void)
+void main(unsigned long bist)
 {
-       msr_t msr;
-
-       /* Setup access to the cache for under 1MB. */
-       msr.hi = 0x24fffc02;
-       msr.lo = 0x1000A000;    /* 0-A0000 write back */
-       wrmsr(CPU_RCONF_DEFAULT, msr);
-
-       msr.hi = 0x0;           /* write back */
-       msr.lo = 0x0;
-       wrmsr(CPU_RCONF_A0_BF, msr);
-       wrmsr(CPU_RCONF_C0_DF, msr);
-       wrmsr(CPU_RCONF_E0_FF, msr);
-
-       /* Setup access to the cache for under 640K. Note MC not setup yet. */
-       msr.hi = 0x20000000;
-       msr.lo = 0xfff80;
-       wrmsr(MSR_GLIU0 + 0x20, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0x80fffe0;
-       wrmsr(MSR_GLIU0 + 0x21, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0xfff80;
-       wrmsr(MSR_GLIU1 + 0x20, msr);
-
-       msr.hi = 0x20000000;
-       msr.lo = 0x80fffe0;
-       wrmsr(MSR_GLIU1 + 0x21, msr);
-}
-
-static void mb_gpio_init(void)
-{
-       /* Early mainboard specific GPIO setup. */
-}
-
-void cache_as_ram_main(void)
-{
-       POST_CODE(0x01);
+       post_code(0x01);
 
        static const struct mem_controller memctrl[] = {
-               {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+               {.channel0 = {DIMM0, DIMM1}}
        };
 
        SystemPreInit();
@@ -114,21 +70,20 @@ void cache_as_ram_main(void)
        /* cs5536_disable_internal_uart: disable them for now, set them
         * up later...
         */
-       /* If debug. real setup done in chipset init via Config.lb. */
+       /* If debug. real setup done in chipset init via devicetree.cb. */
        cs5536_setup_onchipuart(1);
-       mb_gpio_init();
        uart_init();
        console_init();
 
+       /* Halt if there was a built in self test failure */
+       report_bist_failure(bist);
+
        pll_reset(ManualConf);
 
-       cpuRegInit();
+       cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory. */
-       /* ram_check(0x00000000, 640 * 1024); */
-
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }