Drop per-board ram_check() calls for now.

[coreboot.git] / src / mainboard / amd / norwich / romstage.c

diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index 1211610421030da224f3263cce5c41f73e362963..f60313842aa03e1d3fa0d740b86c0de8cf4b0f4e 100644 (file)
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -31,7 +31,6 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 
@@ -52,17 +51,12 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/model_lx/syspreinit.c"
 #include "cpu/amd/model_lx/msrinit.c"
 
-static void mb_gpio_init(void)
-{
-       /* Early mainboard specific GPIO setup. */
-}
-
 void main(unsigned long bist)
 {
        post_code(0x01);
 
        static const struct mem_controller memctrl[] = {
-               {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
+               {.channel0 = {DIMM0, DIMM1}}
        };
 
        SystemPreInit();
@@ -78,7 +72,6 @@ void main(unsigned long bist)
         */
        /* If debug. real setup done in chipset init via devicetree.cb. */
        cs5536_setup_onchipuart(1);
-       mb_gpio_init();
        uart_init();
        console_init();
 
@@ -91,10 +84,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory. */
-       /* ram_check(0x00000000, 640 * 1024); */
-
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }
-