* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
#include <string.h>
#include <stdint.h>
-
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs780[11];
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
-extern u32 bus_type[256];
extern u32 sbdn_rs780;
extern u32 sbdn_sb700;
-extern void get_bus_conf(void);
-
-void *smp_write_config_table(void *v)
+static void *smp_write_config_table(void *v)
{
- static const char sig[4] = "PCMP";
- static const char oem[8] = "AMD ";
- static const char productid[12] = "MAHOGANY ";
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
- memset(mc, 0, sizeof(*mc));
-
- memcpy(mc->mpc_signature, sig, sizeof(sig));
- mc->mpc_length = sizeof(*mc); /* initially just the header */
- mc->mpc_spec = 0x04;
- mc->mpc_checksum = 0; /* not yet computed */
- memcpy(mc->mpc_oem, oem, sizeof(oem));
- memcpy(mc->mpc_productid, productid, sizeof(productid));
- mc->mpc_oemptr = 0;
- mc->mpc_oemsize = 0;
- mc->mpc_entry_count = 0; /* No entries yet... */
- mc->mpc_lapic = LAPIC_ADDR;
- mc->mpe_length = 0;
- mc->mpe_checksum = 0;
- mc->reserved = 0;
+
+ mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
- smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
- IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb700, 0x0);
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- /* ISA ints are edge-triggered, and usually originate from the ISA bus,
- * or its remainings.
- */
-#define ISA_INT(intr, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, (intr), apicid_sb700, (pin))
-
- ISA_INT(0x1, 0x1);
- ISA_INT(0x0, 0x2);
- ISA_INT(0x3, 0x3);
- ISA_INT(0x4, 0x4);
- ISA_INT(0x6, 0x6);
- ISA_INT(0x7, 0x7);
- ISA_INT(0xc, 0xc);
- ISA_INT(0xd, 0xd);
- ISA_INT(0xe, 0xe);
+ mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
#define PCI_INT(bus, dev, fn, pin)
#endif
+ /* changes added to match acpi tables */
+ PCI_INT(0x0, 0x02, 0x0, 0x12);
+ PCI_INT(0x0, 0x03, 0x0, 0x13);
+ PCI_INT(0x0, 0x04, 0x0, 0x10);
+ PCI_INT(0x0, 0x09, 0x0, 0x11);
+ PCI_INT(0x0, 0x0A, 0x0, 0x12);
+ PCI_INT(0x0, 0x12, 0x2, 0x12);
+ PCI_INT(0x0, 0x12, 0x3, 0x13);
+ PCI_INT(0x0, 0x13, 0x2, 0x10);
+ PCI_INT(0x0, 0x13, 0x2, 0x11);
+ PCI_INT(0x0, 0x14, 0x1, 0x11);
+ PCI_INT(0x0, 0x14, 0x3, 0x13);
+ PCI_INT(0x1, 0x05, 0x2, 0x10);
+ PCI_INT(0x1, 0x05, 0x3, 0x11);
+ PCI_INT(0x2, 0x00, 0x0, 0x12);
+ PCI_INT(0x2, 0x00, 0x1, 0x13);
+ PCI_INT(0x2, 0x00, 0x2, 0x10);
+ PCI_INT(0x2, 0x00, 0x3, 0x11);
+
+ /* RS780 PCI to PCI bridge (PCIE port 4) */
+ PCI_INT(0x0, 0x09, 0x0, 0x11);
+
/* usb */
- PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
+ PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
- /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
+ PCI_INT(0x0, 0x14, 0x2, 0x12);
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
-/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
- PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
+ /* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
+ PCI_INT(0x1, 0x5, 0x0, 0x12); /* VGA */
+ PCI_INT(0x1, 0x5, 0x1, 0x13); /* Audio */
+ /* PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); *//* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
- PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
+ /* PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); */
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
- PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
- PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
+ /* PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); */
+ PCI_INT(0x3, 0x0, 0x0, 0x11); /* NIC */
+ /* PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); NIC */
/* PCI slots */
/* PCI_SLOT 0. */
/* There is no extension information... */
/* Compute the checksums */
- mc->mpe_checksum =
- smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
- mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
- printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
- mc, smp_next_mpe_entry(mc));
- return smp_next_mpe_entry(mc);
+ return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
- v = smp_write_floating_table(addr);
+ v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}
projects / coreboot.git / blobdiff