AMD F14 southbridge update

[coreboot.git] / src / mainboard / amd / inagua / romstage.c

diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 57953bce6a023914ca1073459e64b745488a6bdd..c4e8b153a5d9dd9befa72a34380bf6d199ece52b 100644 (file)
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -33,7 +33,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "pc80/i8254.c"
 #include "pc80/i8259.c"
-#include "SbEarly.h"
+#include "sb_cimx.h"
 #include "SBPLATFORM.h"
 #include <arch/cpu.h>
 
@@ -52,7 +52,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
   if (!cpu_init_detectedx && boot_cpu()) {
     post_code(0x30);
-    sb_poweron_init();
+    sb_Poweron_Init();
 
     post_code(0x31);
     kbc1100_early_init(CONFIG_SIO_PORT);