- Bump the LinuxBIOS major version

[coreboot.git] / src / mainboard / Iwill / DK8X / Config.lb

diff --git a/src/mainboard/Iwill/DK8X/Config.lb b/src/mainboard/Iwill/DK8X/Config.lb
index c974bdead1898773a55c5f17d4f06ec5916ff284..f95725ecbbe0e714dbe5d6d33da8546b2fa90a24 100644 (file)
--- a/src/mainboard/Iwill/DK8X/Config.lb
+++ b/src/mainboard/Iwill/DK8X/Config.lb
@@ -239,65 +239,73 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
 dir /pc80
 config chip.h
 
-northbridge amd/amdk8 "mc0"
-       pci 0:18.0
-       pci 0:18.0
-       pci 0:18.0
-       pci 0:18.1
-       pci 0:18.2
-       pci 0:18.3
-       southbridge amd/amd8131 "amd8131" link 0
-               pci 0:0.0
-               pci 0:0.1
-               pci 0:1.0
-               pci 0:1.1
-       end
-       southbridge amd/amd8111 "amd8111" link 0
-               pci 0:0.0
-               pci 0:1.0 on
-               pci 0:1.1 on
-               pci 0:1.2 on
-               pci 0:1.3 on
-               pci 0:1.5 off
-               pci 0:1.6 off
-               pci 1:0.0 on
-               pci 1:0.1 on
-               pci 1:0.2 on
-               pci 1:1.0 off
-               superio winbond/w83627thf link 1
-                       pnp 2e.0
-                       pnp 2e.1
-                       pnp 2e.2
-                       pnp 2e.3
-                       pnp 2e.4
-                       pnp 2e.5
-                       pnp 2e.6
-                       pnp 2e.7
-                       pnp 2e.8
-                       pnp 2e.9
-                       pnp 2e.a
-                       register "com1" = "{1, 0, 0x3f8, 4}"
-                       register "lpt" = "{1}"
+chip northbridge/amd/amdk8
+       device pci_domain 0 on
+               device pci 18.0 on #  northbridge 
+                       #  devices on link 0, link 0 == LDT 0 
+                       chip southbridge/amd/amd8131
+                               # the on/off keyword is mandatory
+                               device pci 0.0 on end
+                               device pci 0.1 on end
+                               device pci 1.0 on end
+                               device pci 1.1 on end
+                       end
+                       chip southbridge/amd/amd8111
+                               # this "device pci 0.0" is the parent the next one
+                               # PCI bridge
+                               device pci 0.0 on
+                                       device pci 0.0 on end
+                                       device pci 0.1 on end
+                                       device pci 0.2 on end
+                                       device pci 1.0 off end
+                               end
+                               device pci 1.0 on
+                                       chip superio/winbond/w83627thf
+                                               device pnp 2e.0 on end
+                                               device pnp 2e.1 on end
+                                               device pnp 2e.2 on end
+                                               device pnp 2e.3 on end
+                                               device pnp 2e.4 on end
+                                               device pnp 2e.5 on end
+                                               device pnp 2e.6 on end
+                                               device pnp 2e.7 on end 
+                                               device pnp 2e.8 on end 
+                                               device pnp 2e.9 on end 
+                                               device pnp 2e.a on end 
+                                       end
+                               end
+                               device pci 1.1 on end
+                               device pci 1.2 on end
+                               device pci 1.3 on end 
+                               device pci 1.5 off end
+                               device pci 1.6 off end
+                       end
+               end # LDT0
+               device pci 18.0 on end # LDT1
+               device pci 18.0 on end # LDT2
+               device pci 18.1 on end
+               device pci 18.2 on end
+               device pci 18.3 on end
+
+               chip northbridge/amd/amdk8
+                       device pci 19.0 on end
+                       device pci 19.0 on end
+                       device pci 19.0 on end
+                       device pci 19.1 on end
+                       device pci 19.2 on end
+                       device pci 19.3 on end
+               end
+       end 
+       device apic_cluster 0 on
+               chip cpu/amd/socket_940
+                       device apic 0 on end
+               end
+               chip cpu/amd/socket_940
+                       device apic 1 on end
                end
        end
 end
 
-northbridge amd/amdk8 "mc1"
-       pci 0:19.0
-       pci 0:19.0
-       pci 0:19.0
-       pci 0:19.1
-       pci 0:19.2
-       pci 0:19.3
-end
-
-cpu k8 "cpu0"
-       register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
-end
-
-cpu k8 "cpu1" 
-end
-
 ##
 ## Include the old serial code for those few places that still need it.
 ##