added initial uart_rx files, not exaustively tested though.

[hwmod.git] / src / history.vhd

diff --git a/src/history.vhd b/src/history.vhd
index cd6dbcda6e6f2fc7e3a7a79b26256c56ed999e2f..1c69612edb72fd9c0a72091890433600cbae353e 100644 (file)
--- a/src/history.vhd
+++ b/src/history.vhd
@@ -102,12 +102,12 @@ begin
                case state_int is
                        when SIDLE =>
                                -- S_S_FIN: tmp..
-                               if d_get = '1' then
-                                       state_next <= S_D_INIT;
+                               if s_take = '1' then
+                                       state_next <= S_S_INIT;
                                elsif do_it = '1' then
                                        state_next <= S_S_FIN;
-                               elsif s_take = '1' then
-                                       state_next <= S_S_INIT;
+                               elsif d_get = '1' then
+                                       state_next <= S_D_INIT;
                                end if;
                        when S_S_INIT =>
                                if s_backspace = '1' then
@@ -139,12 +139,12 @@ begin
 
        -- out
        process(state_int, s_cnt_int, d_spalte, data_out, s_char, address_int,
-               data_in_int)
+               data_in_int, d_new_result_int, d_new_eingabe_int)
        begin
                s_done_next <= '0';
                s_cnt_next <= s_cnt_int;
-               d_new_result_next <= '0';
-               d_new_eingabe_next <= '0';
+               d_new_result_next <= d_new_result_int;
+               d_new_eingabe_next <= d_new_eingabe_int;
                d_done_next <= '0';
                d_char_next <= (others => '0');
                finished_next <= '0';
@@ -159,12 +159,12 @@ begin
                                null;
                        when S_S_WRITE =>
                                wr_next <= '1';
-                               address_next <= '0' & s_cnt_int;
+                               address_next <= s_cnt_int;
                                data_in_next <= s_char;
                                s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
                        when S_S_BS =>
                                wr_next <= '1';
-                               address_next <= '0' & std_logic_vector(unsigned(s_cnt_int) - 1);
+                               address_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
                                data_in_next <= (others => '0');
                                if unsigned(s_cnt_int) /= 0 then
                                        s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
@@ -178,7 +178,9 @@ begin
                                d_new_eingabe_next <= '1';
 
                        when S_D_INIT =>
-                               address_next <= '0' & d_spalte;
+                               address_next <= d_spalte;
+                               d_new_eingabe_next <= '0';
+                               d_new_result_next <= '0';
                        when S_D_WAIT =>
                                null;
                        when S_D_WRITE =>