pc_zeile : in hzeile;
pc_char : out hbyte;
pc_done : out std_logic;
- pc_busy : out std_logic;
-- Scanner
s_char : in hbyte;
s_take : in std_logic;
architecture beh of history is
type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE,
- S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_DUMMY ,S_PC_READ);
+ S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_READ);
signal state_int, state_next : HISTORY_STATE;
signal was_bs_int, was_bs_next : std_logic;
signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
signal p_sp_write_int, p_sp_write_next : hspalte;
signal pc_char_next ,pc_char_int : hbyte;
signal pc_done_next, pc_done_int : std_logic;
- signal pc_busy_next, pc_busy_int : std_logic;
-- ram
signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
p_wdone <= p_wdone_int;
p_read <= p_read_int;
pc_done <= pc_done_int;
- pc_busy <= pc_busy_int;
pc_char <= pc_char_int;
process(sys_clk, sys_res_n)
pc_char_int <= (others => '0');
pc_done_int <= '0';
- pc_busy_int <= '0';
address_int <= (0 => '1', others => '0');
data_in_int <= x"00";
pc_char_int <= pc_char_next;
pc_done_int <= pc_done_next;
- pc_busy_int <= pc_busy_next;
address_int <= address_next;
data_in_int <= data_in_next;
state_next <= SIDLE;
end if;
when S_PC_INIT =>
- state_next <= S_PC_DUMMY;
- when S_PC_DUMMY =>
state_next <= S_PC_READ;
when S_PC_READ =>
if pc_get = '0' then
data_in_next <= data_in_int;
pc_done_next <= '0';
pc_char_next <= pc_char_int;
- pc_busy_next <= '0';
p_rdone_next <= p_rdone_int;
p_wdone_next <= p_wdone_int;
p_read_next <= p_read_int;
when S_D_INIT =>
addr_tmp := (others => '0');
addr_tmp(hzeile'length - 1 downto 0) := d_zeile;
- mul_tmp := std_logic_vector(unsigned(addr_tmp) *
- to_unsigned(HSPALTE_MAX,H_RAM_WIDTH));
+ mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(HSPALTE_MAX,H_RAM_WIDTH));
addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte));
address_next <= addr_tmp;
addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte));
address_next <= addr_tmp;
- pc_busy_next <= '1';
- when S_PC_DUMMY =>
- pc_busy_next <= '1';
when S_PC_READ =>
- pc_char_next <= data_out;
pc_done_next <= '1';
+ pc_char_next <= data_out;
+
when S_P_READ =>
wr_next <= '0';
spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1);
end case;
end process;
- sp_ram_inst : entity work.sp_ram(beh)
+ sp_ram_inst : sp_ram
generic map (
ADDR_WIDTH => H_RAM_WIDTH
)