static int uart_can_tx_byte(void)
{
- return inb(TTYS0_BASE + UART_LSR) & 0x20;
+ return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
}
static void uart_wait_to_tx_byte(void)
static void uart_wait_until_sent(void)
{
- while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
+ while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
;
}
static void uart_tx_byte(unsigned char data)
{
uart_wait_to_tx_byte();
- outb(data, TTYS0_BASE + UART_TBR);
+ outb(data, CONFIG_TTYS0_BASE + UART_TBR);
/* Make certain the data clears the fifos */
uart_wait_until_sent();
}
void smi_handler(u32 smm_revision)
{
- u8 reg8;
- u16 pmctrl;
- u16 pm1_sts;
- u32 smi_sts, gpe0_sts, tco_sts;
unsigned int node;
smm_state_save_area_t state_save;
node=nodeid();
#ifdef DEBUG_SMI
- console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
+ console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
#else
console_loglevel = 1;
#endif
- printk_debug("\nSMI# #%d\n", node);
+ printk_spew("\nSMI# #%d\n", node);
switch (smm_revision) {
case 0x00030007:
return;
}
+ /* Call chipset specific SMI handlers. This would be the place to
+ * add a CPU or northbridge specific SMI handler, too
+ */
+
southbridge_smi_handler(node, &state_save);
smi_release_lock();