Get rid of AUTO_XIP_ROM_BASE

[coreboot.git] / src / cpu / x86 / mtrr / earlymtrr.c

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index e8fda994afedf5e49dce6bff6dfa43ee249acc74..f8119d3e597abeb6e3d00800e11a85641d288576 100644 (file)
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -2,63 +2,34 @@
 #define EARLYMTRR_C
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
 #include <cpu/x86/msr.h>
 
-/* Validate XIP_ROM_SIZE and XIP_ROM_BASE */
-#if defined(XIP_ROM_SIZE) && !defined(XIP_ROM_BASE)
-#error "XIP_ROM_SIZE without XIP_ROM_BASE"
-#endif
-#if defined(XIP_ROM_BASE) && !defined(XIP_ROM_SIZE)
-#error "XIP_ROM_BASE without XIP_ROM_SIZE"
-#endif
-#if !defined(CONFIG_LB_MEM_TOPK)
-#error "CONFIG_LB_MEM_TOPK not defined"
-#endif
-
-#if defined(XIP_ROM_SIZE) && ((XIP_ROM_SIZE & (XIP_ROM_SIZE -1)) != 0)
-#error "XIP_ROM_SIZE is not a power of 2"
-#endif
-#if defined(XIP_ROM_SIZE) && ((XIP_ROM_BASE % XIP_ROM_SIZE) != 0)
-#error "XIP_ROM_BASE is not a multiple of XIP_ROM_SIZE"
-#endif
-
-#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
-# error "CONFIG_LB_MEM_TOPK must be a power of 2"
-#endif
-
-static void disable_var_mtrr(unsigned reg)
-{
-       /* The invalid bit is kept in the mask so we simply
-        * clear the relevent mask register to disable a
-        * range.
-        */
-       msr_t zero;
-       zero.lo = zero.hi = 0;
-       wrmsr(MTRRphysMask_MSR(reg), zero);
-}
-
 static void set_var_mtrr(
        unsigned reg, unsigned base, unsigned size, unsigned type)
 
 {
        /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+       /* FIXME: It only support 4G less range */
        msr_t basem, maskm;
        basem.lo = base | type;
        basem.hi = 0;
        wrmsr(MTRRphysBase_MSR(reg), basem);
-       maskm.lo = ~(size - 1) | 0x800;
-       maskm.hi = 0x0f;
+       maskm.lo = ~(size - 1) | MTRRphysMaskValid;
+       maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
        wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
 
+#if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0)
 static void cache_lbmem(int type)
 {
        /* Enable caching for 0 - 1MB using variable mtrr */
        disable_cache();
-       set_var_mtrr(0, 0x00000000, CONFIG_LB_MEM_TOPK << 10, type);
+       set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, type);
        enable_cache();
 }
 
+const int addr_det = 0;
 
 /* the fixed and variable MTTRs are power-up with random values,
  * clear them to MTRR_TYPE_UNCACHEABLE for safty.
@@ -71,9 +42,6 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
         */
        msr_t msr;
        const unsigned long *msr_addr;
-       unsigned long cr0;
-
-       print_spew("Clearing mtrr\r\n");
 
        /* Inialize all of the relevant msrs to 0 */
        msr.lo = 0;
@@ -83,23 +51,26 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
                wrmsr(msr_nr, msr);
        }
 
-#if defined(XIP_ROM_SIZE)
+#if defined(CONFIG_XIP_ROM_SIZE)
        /* enable write through caching so we can do execute in place
         * on the flash rom.
+        * Determine address by calculating the XIP_ROM_SIZE sized area with
+        * XIP_ROM_SIZE alignment that contains the global variable defined above;
         */
-       set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
+        unsigned long f = (unsigned long)&addr_det & ~(CONFIG_XIP_ROM_SIZE - 1);
+       set_var_mtrr(1, f, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
 #endif
 
-       /* Set the default memory type and enable fixed and variable MTRRs 
+       /* Set the default memory type and enable fixed and variable MTRRs
         */
        /* Enable Variable MTRRs */
        msr.hi = 0x00000000;
        msr.lo = 0x00000800;
        wrmsr(MTRRdefType_MSR, msr);
-       
+
 }
 
-static void early_mtrr_init(void)
+static inline void early_mtrr_init(void)
 {
        static const unsigned long mtrr_msrs[] = {
                /* fixed mtrr */
@@ -120,4 +91,18 @@ static void early_mtrr_init(void)
        enable_cache();
 }
 
+static inline int early_mtrr_init_detected(void)
+{
+       msr_t msr;
+       /* See if MTRR's are enabled.
+        * a #RESET disables them while an #INIT
+        * preserves their state.  This works
+        * on both Intel and AMD cpus, at least
+        * according to the documentation.
+        */
+       msr = rdmsr(MTRRdefType_MSR);
+       return msr.lo & MTRRdefTypeEn;
+}
+#endif
+
 #endif /* EARLYMTRR_C */