Get rid of AUTO_XIP_ROM_BASE

[coreboot.git] / src / cpu / x86 / mtrr / earlymtrr.c

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 8a7ecbc54c2dba7412e3918759378e5100d8d5d8..f8119d3e597abeb6e3d00800e11a85641d288576 100644 (file)
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -2,21 +2,9 @@
 #define EARLYMTRR_C
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
 #include <cpu/x86/msr.h>
 
-#if 0
-static void disable_var_mtrr(unsigned reg)
-{
-       /* The invalid bit is kept in the mask so we simply
-        * clear the relevent mask register to disable a
-        * range.
-        */
-       msr_t zero;
-       zero.lo = zero.hi = 0;
-       wrmsr(MTRRphysMask_MSR(reg), zero);
-}
-#endif
-
 static void set_var_mtrr(
        unsigned reg, unsigned base, unsigned size, unsigned type)
 
@@ -27,32 +15,12 @@ static void set_var_mtrr(
        basem.lo = base | type;
        basem.hi = 0;
        wrmsr(MTRRphysBase_MSR(reg), basem);
-       maskm.lo = ~(size - 1) | 0x800;
-       maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1;
+       maskm.lo = ~(size - 1) | MTRRphysMaskValid;
+       maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
        wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
 
-#if 0
-static void set_var_mtrr_x(
-        unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type)
-
-{
-        /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
-        msr_t basem, maskm;
-        basem.lo = (base_lo & 0xfffff000) | type;
-        basem.hi = base_hi & ((1<<(CONFIG_CPU_ADDR_BITS-32))-1);
-        wrmsr(MTRRphysBase_MSR(reg), basem);
-               maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1;
-       if(size_lo) {
-               maskm.lo = ~(size_lo - 1) | 0x800;
-       } else {
-               maskm.lo = 0x800;
-               maskm.hi &= ~(size_hi - 1);
-       }
-        wrmsr(MTRRphysMask_MSR(reg), maskm);
-}
-#endif
-
+#if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0)
 static void cache_lbmem(int type)
 {
        /* Enable caching for 0 - 1MB using variable mtrr */
@@ -61,6 +29,8 @@ static void cache_lbmem(int type)
        enable_cache();
 }
 
+const int addr_det = 0;
+
 /* the fixed and variable MTTRs are power-up with random values,
  * clear them to MTRR_TYPE_UNCACHEABLE for safty.
  */
@@ -84,20 +54,23 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
 #if defined(CONFIG_XIP_ROM_SIZE)
        /* enable write through caching so we can do execute in place
         * on the flash rom.
+        * Determine address by calculating the XIP_ROM_SIZE sized area with
+        * XIP_ROM_SIZE alignment that contains the global variable defined above;
         */
-       set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
+        unsigned long f = (unsigned long)&addr_det & ~(CONFIG_XIP_ROM_SIZE - 1);
+       set_var_mtrr(1, f, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
 #endif
 
-       /* Set the default memory type and enable fixed and variable MTRRs 
+       /* Set the default memory type and enable fixed and variable MTRRs
         */
        /* Enable Variable MTRRs */
        msr.hi = 0x00000000;
        msr.lo = 0x00000800;
        wrmsr(MTRRdefType_MSR, msr);
-       
+
 }
 
-static void early_mtrr_init(void)
+static inline void early_mtrr_init(void)
 {
        static const unsigned long mtrr_msrs[] = {
                /* fixed mtrr */
@@ -118,7 +91,7 @@ static void early_mtrr_init(void)
        enable_cache();
 }
 
-static int early_mtrr_init_detected(void)
+static inline int early_mtrr_init_detected(void)
 {
        msr_t msr;
        /* See if MTRR's are enabled.
@@ -128,7 +101,8 @@ static int early_mtrr_init_detected(void)
         * according to the documentation.
         */
        msr = rdmsr(MTRRdefType_MSR);
-       return msr.lo & 0x00000800;
+       return msr.lo & MTRRdefTypeEn;
 }
+#endif
 
 #endif /* EARLYMTRR_C */