This patch unifies the use of config options in v2 to all start with CONFIG_

[coreboot.git] / src / cpu / x86 / mtrr / earlymtrr.c

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 105f7c49df25336854bd457ea7a33352a32d5024..cff99b8964e55a884455291f259e03b3222caafa 100644 (file)
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -4,22 +4,22 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 
-/* Validate XIP_ROM_SIZE and XIP_ROM_BASE */
-#if defined(XIP_ROM_SIZE) && !defined(XIP_ROM_BASE)
-# error "XIP_ROM_SIZE without XIP_ROM_BASE"
+/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
+#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
+# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
 #endif
-#if defined(XIP_ROM_BASE) && !defined(XIP_ROM_SIZE)
-# error "XIP_ROM_BASE without XIP_ROM_SIZE"
+#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
+# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
 #endif
 #if !defined(CONFIG_LB_MEM_TOPK)
 # error "CONFIG_LB_MEM_TOPK not defined"
 #endif
 
-#if defined(XIP_ROM_SIZE) && ((XIP_ROM_SIZE & (XIP_ROM_SIZE -1)) != 0)
-# error "XIP_ROM_SIZE is not a power of 2"
+#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
+# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
 #endif
-#if defined(XIP_ROM_SIZE) && ((XIP_ROM_BASE % XIP_ROM_SIZE) != 0)
-# error "XIP_ROM_BASE is not a multiple of XIP_ROM_SIZE"
+#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
+# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
 #endif
 
 #if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
@@ -42,15 +42,35 @@ static void set_var_mtrr(
 
 {
        /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+       /* FIXME: It only support 4G less range */
        msr_t basem, maskm;
        basem.lo = base | type;
        basem.hi = 0;
        wrmsr(MTRRphysBase_MSR(reg), basem);
        maskm.lo = ~(size - 1) | 0x800;
-       maskm.hi = 0x0f;
+       maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1;
        wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
 
+static void set_var_mtrr_x(
+        unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type)
+
+{
+        /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+        msr_t basem, maskm;
+        basem.lo = (base_lo & 0xfffff000) | type;
+        basem.hi = base_hi & ((1<<(CONFIG_CPU_ADDR_BITS-32))-1);
+        wrmsr(MTRRphysBase_MSR(reg), basem);
+               maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1;
+       if(size_lo) {
+               maskm.lo = ~(size_lo - 1) | 0x800;
+       } else {
+               maskm.lo = 0x800;
+               maskm.hi &= ~(size_hi - 1);
+       }
+        wrmsr(MTRRphysMask_MSR(reg), maskm);
+}
+
 static void cache_lbmem(int type)
 {
        /* Enable caching for 0 - 1MB using variable mtrr */
@@ -70,7 +90,6 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
         */
        msr_t msr;
        const unsigned long *msr_addr;
-       unsigned long cr0;
 
        /* Inialize all of the relevant msrs to 0 */
        msr.lo = 0;
@@ -80,11 +99,11 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
                wrmsr(msr_nr, msr);
        }
 
-#if defined(XIP_ROM_SIZE)
+#if defined(CONFIG_XIP_ROM_SIZE)
        /* enable write through caching so we can do execute in place
         * on the flash rom.
         */
-       set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
+       set_var_mtrr(1, CONFIG_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
 #endif
 
        /* Set the default memory type and enable fixed and variable MTRRs 
@@ -117,4 +136,17 @@ static void early_mtrr_init(void)
        enable_cache();
 }
 
+static int early_mtrr_init_detected(void)
+{
+       msr_t msr;
+       /* See if MTRR's are enabled.
+        * a #RESET disables them while an #INIT
+        * preserves their state.  This works
+        * on both Intel and AMD cpus, at least
+        * according to the documentation.
+        */
+       msr = rdmsr(MTRRdefType_MSR);
+       return msr.lo & 0x00000800;
+}
+
 #endif /* EARLYMTRR_C */