Add an option to keep the ROM cached after romstage

[coreboot.git] / src / cpu / x86 / Kconfig

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index ec559b504314b1556c74c603554e3c84b77a38e0..68946227b96a30967a5ca935ab460b371feb2683 100644 (file)
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -19,16 +19,17 @@ config UDELAY_TSC
        bool
        default n
 
-config TSC_CALIBRATE_WITH_IO
+config UDELAY_TIMER2
        bool
        default n
 
-config XIP_ROM_BASE
-       hex
-       default 0xffff0000
+config TSC_CALIBRATE_WITH_IO
+       bool
+       default n
 
 config XIP_ROM_SIZE
        hex
+       default ROM_SIZE if ROMCC
        default 0x10000
 
 config CPU_ADDR_BITS
@@ -39,4 +40,6 @@ config LOGICAL_CPUS
        bool
        default y
 
-
+config CACHE_ROM
+       bool
+       default n