This patch unifies the use of config options in v2 to all start with CONFIG_

[coreboot.git] / src / cpu / via / car / cache_as_ram_post.c

diff --git a/src/cpu/via/car/cache_as_ram_post.c b/src/cpu/via/car/cache_as_ram_post.c
index 9058727bc622fe1c1dadd3fd9f6a657914ecd38e..3c5c5e486bc8f58712cd8cc3037b093d87356ec8 100644 (file)
--- a/src/cpu/via/car/cache_as_ram_post.c
+++ b/src/cpu/via/car/cache_as_ram_post.c
@@ -78,16 +78,16 @@ and in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.*/
                                "movl    $((~(( 0 + 0x40000) - 1)) | 0x800), %eax\n\t"
         "wrmsr\n\t"        
         
-       /*jasonzhao@viatech.com.cn add this 2008-11-27, cache XIP_ROM_BASE-SIZE to speedup the coreboot code*/
+       /*jasonzhao@viatech.com.cn add this 2008-11-27, cache CONFIG_XIP_ROM_BASE-SIZE to speedup the coreboot code*/
                                "movl    $0x206, %ecx\n\t"
         "xorl    %edx, %edx\n\t"
-        "movl     $XIP_ROM_BASE,%eax\n\t"
+        "movl     $CONFIG_XIP_ROM_BASE,%eax\n\t"
         "orl     $(0 | 6), %eax\n\t"
         "wrmsr\n\t"
 
                                "movl    $0x207, %ecx\n\t"
         "xorl    %edx, %edx\n\t"
-        "movl     $XIP_ROM_SIZE,%eax\n\t"
+        "movl     $CONFIG_XIP_ROM_SIZE,%eax\n\t"
         "decl  %eax\n\t"
         "notl  %eax\n\t"
         "orl     $(0 | 0x800), %eax\n\t"