#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
+#include <console/post_codes.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase CONFIG_DCACHE_RAM_BASE
/* Clear all MTRRs. */
xorl %edx, %edx
- movl $fixed_mtrr_msr, %esi
+ movl $all_mtrr_msrs, %esi
clear_fixed_var_mtrr:
lodsl (%esi), %eax
jmp clear_fixed_var_mtrr
-fixed_mtrr_msr:
- .long 0x250, 0x258, 0x259
- .long 0x268, 0x269, 0x26A
- .long 0x26B, 0x26C, 0x26D
- .long 0x26E, 0x26F
-
-var_mtrr_msr:
- .long 0x200, 0x201, 0x202, 0x203
- .long 0x204, 0x205, 0x206, 0x207
- .long 0x208, 0x209, 0x20A, 0x20B
- .long 0x20C, 0x20D, 0x20E, 0x20F
+all_mtrr_msrs:
+ /* fixed MTRR MSRs */
+ .long MTRRfix64K_00000_MSR
+ .long MTRRfix16K_80000_MSR
+ .long MTRRfix16K_A0000_MSR
+ .long MTRRfix4K_C0000_MSR
+ .long MTRRfix4K_C8000_MSR
+ .long MTRRfix4K_D0000_MSR
+ .long MTRRfix4K_D8000_MSR
+ .long MTRRfix4K_E0000_MSR
+ .long MTRRfix4K_E8000_MSR
+ .long MTRRfix4K_F0000_MSR
+ .long MTRRfix4K_F8000_MSR
+
+ /* var MTRR MSRs */
+ .long MTRRphysBase_MSR(0)
+ .long MTRRphysMask_MSR(0)
+ .long MTRRphysBase_MSR(1)
+ .long MTRRphysMask_MSR(1)
+ .long MTRRphysBase_MSR(2)
+ .long MTRRphysMask_MSR(2)
+ .long MTRRphysBase_MSR(3)
+ .long MTRRphysMask_MSR(3)
+ .long MTRRphysBase_MSR(4)
+ .long MTRRphysMask_MSR(4)
+ .long MTRRphysBase_MSR(5)
+ .long MTRRphysMask_MSR(5)
+ .long MTRRphysBase_MSR(6)
+ .long MTRRphysMask_MSR(6)
+ .long MTRRphysBase_MSR(7)
+ .long MTRRphysMask_MSR(7)
+
.long 0x000 /* NULL, end of table */
clear_fixed_var_mtrr_out:
movl $MTRRphysMask_MSR(0), %ecx
/* This assumes we never access addresses above 2^36 in CAR. */
movl $0x0000000f, %edx
- movl $(~(CacheSize - 1) | 0x800), %eax
+ movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax
wrmsr
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
-
/*
* Enable write base caching so we can do execute in place (XIP)
* on the flash ROM.
*/
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
- movl $REAL_XIP_ROM_BASE, %eax
+ /*
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
+ * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ */
+ movl $copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
movl $0x0000000f, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
/* Set the default memory type and enable fixed and variable MTRRs. */
rep stosl
#ifdef CARTEST
- movl REAL_XIP_ROM_BASE, %esi
+ /*
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
+ * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ */
+ movl $copy_and_run, %esi
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %ei
movl %esi, %edi
movl $(CONFIG_XIP_ROM_SIZE >> 2), %ecx
rep lodsl
movl $(MTRRdefTypeEn), %eax
wrmsr
- /* Enable caching for first 1M using variable MTRR. */
+ /* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */
movl $MTRRphysBase_MSR(0), %ecx
xorl %edx, %edx
- movl $(0 | MTRR_TYPE_WRBACK), %eax
+ movl $(CONFIG_RAMBASE | MTRR_TYPE_WRBACK), %eax
wrmsr
- /*
- * Enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
- * If 1M cacheable, then when S3 resume, there is stange color on
- * screen for 2 sec. Suppose problem of a0000-dfffff and cache.
- * And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.
- */
-
movl $MTRRphysMask_MSR(0), %ecx
movl $0x0000000f, %edx /* AMD 40 bit 0xff */
- movl $((~((0 + 0x80000) - 1)) | 0x800), %eax
+ movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax
wrmsr
+ /* Cache XIP_ROM area to speedup coreboot code. */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
- movl $(0x80000 | MTRR_TYPE_WRBACK), %eax
- wrmsr
-
- movl $MTRRphysMask_MSR(1), %ecx
- movl $0x0000000f, %edx /* AMD 40 bit 0xff */
- movl $((~((0 + 0x20000) - 1)) | 0x800), %eax
- wrmsr
-
- movl $MTRRphysBase_MSR(2), %ecx
- xorl %edx, %edx
- movl $(0xc0000 | MTRR_TYPE_WRBACK), %eax
- wrmsr
-
- movl $MTRRphysMask_MSR(2), %ecx
- movl $0x0000000f, %edx /* AMD 40 bit 0xff */
- movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax
- wrmsr
-
- /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
- movl $MTRRphysBase_MSR(3), %ecx
- xorl %edx, %edx
- movl $REAL_XIP_ROM_BASE, %eax
+ /*
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
+ * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ */
+ movl $copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
- movl $MTRRphysMask_MSR(3), %ecx
+ movl $MTRRphysMask_MSR(1), %ecx
xorl %edx, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
/* Enable cache. */
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
- post_code(0x11)
+ post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
call copy_and_run
.Lhlt:
- post_code(0xee)
+ post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
projects / coreboot.git / blobdiff