Get rid of AUTO_XIP_ROM_BASE

[coreboot.git] / src / cpu / intel / model_6fx / cache_as_ram.inc

diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 3737429325fa8001e7f4c40a6b8ba5a498448ee5..a8690112c83cdd0115080002dc9f696624c8800e 100644 (file)
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -20,6 +20,7 @@
 
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/post_code.h>
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@@ -69,14 +70,14 @@ clear_mtrrs:
 
        /* Set Cache-as-RAM mask. */
        movl    $(MTRRphysMask_MSR(0)), %ecx
-       movl    $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
+       movl    $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
        movl    $0x0000000f, %edx
        wrmsr
 
        /* Enable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       orl     $(1 << 11), %eax
+       orl     $MTRRdefTypeEn, %eax
        wrmsr
 
        /* Enable L2 cache. */
@@ -108,23 +109,18 @@ clear_mtrrs:
        /* Enable cache for our code in Flash because we do XIP here */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
        /*
-        * IMPORTANT: The two lines below can _not_ be written like this:
-        *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
         * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
         */
-       movl    $REAL_XIP_ROM_BASE, %eax
+       movl    copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 
        movl    $MTRRphysMask_MSR(1), %ecx
        movl    $0x0000000f, %edx
-       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
@@ -134,7 +130,7 @@ clear_mtrrs:
        movl    %eax, %cr0
 
        /* Set up the stack pointer. */
-#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
+#if CONFIG_USBDEBUG
        /* Leave some space for the struct ehci_debug_info. */
        movl    $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
 #else
@@ -166,7 +162,7 @@ clear_mtrrs:
        /* Disable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       andl    $(~(1 << 11)), %eax
+       andl    $(~MTRRdefTypeEn), %eax
        wrmsr
 
        post_code(0x31)
@@ -207,7 +203,7 @@ clear_mtrrs:
        xorl    %edx, %edx
        wrmsr
        movl    $MTRRphysMask_MSR(0), %ecx
-       movl    $(~(1024 * 1024 - 1) | (1 << 11)), %eax
+       movl    $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
        movl    $0x0000000f, %edx       // 36bit address space
        wrmsr
 
@@ -223,7 +219,7 @@ clear_mtrrs:
        /* Enable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       orl     $(1 << 11), %eax
+       orl     $MTRRdefTypeEn, %eax
        wrmsr
 
        post_code(0x3b)
@@ -243,7 +239,7 @@ clear_mtrrs:
        /* Clear boot_complete flag. */
        xorl    %ebp, %ebp
 __main:
-       post_code(0x11)
+       post_code(POST_PREPARE_RAMSTAGE)
        cld                     /* Clear direction flag. */
 
        movl    %ebp, %esi
@@ -254,7 +250,7 @@ __main:
        call    copy_and_run
 
 .Lhlt:
-       post_code(0xee)
+       post_code(POST_DEAD_CODE)
        hlt
        jmp     .Lhlt