Remove XIP_ROM_BASE

[coreboot.git] / src / cpu / intel / model_6ex / cache_as_ram.inc

diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index fc4947600f740b1063438f0c436f7892c30eea1f..18ada2965b0afbf0fbfa71b85058ddfc7852edbc 100644 (file)
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -63,14 +63,14 @@ clear_mtrrs:
 
        /* Set Cache-as-RAM mask. */
        movl    $(MTRRphysMask_MSR(0)), %ecx
-       movl    $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
+       movl    $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
        movl    $0x0000000f, %edx
        wrmsr
 
        /* Enable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       orl     $(1 << 11), %eax
+       orl     $MTRRdefTypeEn, %eax
        wrmsr
 
        /* Enable L2 cache. */
@@ -98,29 +98,24 @@ clear_mtrrs:
        orl     $(1 << 30), %eax
        movl    %eax, %cr0
 
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE
        /* Enable cache for our code in Flash because we do XIP here */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
        /*
-        * IMPORTANT: The two lines below can _not_ be written like this:
-        *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
         * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
         */
-       movl    $REAL_XIP_ROM_BASE, %eax
+       movl    $copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 
        movl    $MTRRphysMask_MSR(1), %ecx
        movl    $0x0000000f, %edx
-       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
 
        /* Enable cache. */
        movl    %cr0, %eax
@@ -128,7 +123,7 @@ clear_mtrrs:
        movl    %eax, %cr0
 
        /* Set up the stack pointer. */
-#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
+#if CONFIG_USBDEBUG
        /* Leave some space for the struct ehci_debug_info. */
        movl    $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
 #else
@@ -160,7 +155,7 @@ clear_mtrrs:
        /* Disable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       andl    $(~(1 << 11)), %eax
+       andl    $(~MTRRdefTypeEn), %eax
        wrmsr
 
        post_code(0x31)
@@ -201,7 +196,17 @@ clear_mtrrs:
        xorl    %edx, %edx
        wrmsr
        movl    $MTRRphysMask_MSR(0), %ecx
-       movl    $(~(1024 * 1024 - 1) | (1 << 11)), %eax
+       movl    $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+       movl    $0x0000000f, %edx       // 36bit address space
+       wrmsr
+
+       /* Enable caching and Speculative Reads for the last 4MB. */
+       movl    $MTRRphysBase_MSR(1), %ecx
+       movl    $(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+       xorl    %edx, %edx
+       wrmsr
+       movl    $MTRRphysMask_MSR(1), %ecx
+       movl    $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax
        movl    $0x0000000f, %edx       // 36bit address space
        wrmsr
 
@@ -217,7 +222,7 @@ clear_mtrrs:
        /* Enable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       orl     $(1 << 11), %eax
+       orl     $MTRRdefTypeEn, %eax
        wrmsr
 
        post_code(0x3b)