Enable caching for ROM area in model_6ex/cache_as_ram.inc

[coreboot.git] / src / cpu / intel / model_6ex / cache_as_ram.inc

diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 0ee26fcdd2b897e10caae0f9466cbb7d887f6028..02de5ab50ff2f39371a1ada5c2734f8632343c6e 100644 (file)
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -102,7 +102,7 @@ clear_mtrrs:
        /* Enable cache for our code in Flash because we do XIP here */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#if CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
@@ -128,7 +128,7 @@ clear_mtrrs:
        movl    %eax, %cr0
 
        /* Set up the stack pointer. */
-#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
+#if CONFIG_USBDEBUG
        /* Leave some space for the struct ehci_debug_info. */
        movl    $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
 #else
@@ -201,7 +201,17 @@ clear_mtrrs:
        xorl    %edx, %edx
        wrmsr
        movl    $MTRRphysMask_MSR(0), %ecx
-       movl    $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
+       movl    $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+       movl    $0x0000000f, %edx       // 36bit address space
+       wrmsr
+
+       /* Enable caching and Speculative Reads for the last 4MB. */
+       movl    $MTRRphysBase_MSR(1), %ecx
+       movl    $(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+       xorl    %edx, %edx
+       wrmsr
+       movl    $MTRRphysMask_MSR(1), %ecx
+       movl    $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax
        movl    $0x0000000f, %edx       // 36bit address space
        wrmsr