Remove XIP_ROM_BASE

[coreboot.git] / src / cpu / intel / model_106cx / cache_as_ram.inc

diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index b45599ac1b7ea09dc95e4b6e722165052d922030..eb3d650ed258b05e69044591f53fa4ed9c1afc52 100644 (file)
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -98,7 +98,7 @@ clear_mtrrs:
        orl     $(1 << 30), %eax
        movl    %eax, %cr0
 
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE
        /* Enable cache for our code in Flash because we do XIP here */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
@@ -106,7 +106,7 @@ clear_mtrrs:
         * IMPORTANT: The following calculation _must_ be done at runtime. See
         * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
         */
-       movl    copy_and_run, %eax
+       movl    $copy_and_run, %eax
        andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
@@ -115,7 +115,7 @@ clear_mtrrs:
        xorl    %edx, %edx
        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
        wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
 
        /* Enable cache. */
        movl    %cr0, %eax