Intel model_106cx: Use symbolic names for MTRR bits

[coreboot.git] / src / cpu / intel / model_106cx / cache_as_ram.inc

diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index eb3d650ed258b05e69044591f53fa4ed9c1afc52..824e3411100e75b6bcc0dfa5209dbcffb5c9937e 100644 (file)
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -63,14 +63,14 @@ clear_mtrrs:
 
        /* Set Cache-as-RAM mask. */
        movl    $(MTRRphysMask_MSR(0)), %ecx
-       movl    $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
+       movl    $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
        xorl    %edx, %edx
        wrmsr
 
        /* Enable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       orl     $(1 << 11), %eax
+       orl     $MTRRdefTypeEn, %eax
        wrmsr
 
        /* Enable L2 cache. */
@@ -113,7 +113,7 @@ clear_mtrrs:
 
        movl    $MTRRphysMask_MSR(1), %ecx
        xorl    %edx, %edx
-       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE */
 
@@ -155,7 +155,7 @@ clear_mtrrs:
        /* Disable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       andl    $(~(1 << 11)), %eax
+       andl    $(~MTRRdefTypeEn), %eax
        wrmsr
 
        post_code(0x31)
@@ -196,7 +196,7 @@ clear_mtrrs:
        xorl    %edx, %edx
        wrmsr
        movl    $MTRRphysMask_MSR(0), %ecx
-       movl    $(~(1024 * 1024 - 1) | (1 << 11)), %eax
+       movl    $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
        xorl    %edx, %edx
        wrmsr
 
@@ -212,7 +212,7 @@ clear_mtrrs:
        /* Enable MTRR. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       orl     $(1 << 11), %eax
+       orl     $MTRRdefTypeEn, %eax
        wrmsr
 
        post_code(0x3b)