Intel model_106cx: Use symbolic names for MTRR bits

[coreboot.git] / src / cpu / intel / model_106cx / cache_as_ram.inc

diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index 03e0c2671c17cb9cd3c33f86a19436434ba9ed4b..824e3411100e75b6bcc0dfa5209dbcffb5c9937e 100644 (file)
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -18,14 +18,15 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/post_code.h>
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
-       save_bist_result()
+       /* Save the BIST result. */
+       movl    %eax, %ebp
 
 cache_as_ram:
        post_code(0x20)
@@ -62,16 +63,23 @@ clear_mtrrs:
 
        /* Set Cache-as-RAM mask. */
        movl    $(MTRRphysMask_MSR(0)), %ecx
-       movl    $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
+       movl    $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
        xorl    %edx, %edx
        wrmsr
 
-       enable_mtrr()
+       /* Enable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       orl     $MTRRdefTypeEn, %eax
+       wrmsr
 
-       enable_l2_cache()
+       /* Enable L2 cache. */
+       movl    $0x11e, %ecx
+       rdmsr
+       orl     $(1 << 8), %eax
+       wrmsr
 
        /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
-       /* TODO: enable_cache()? But that doesn't have "invd". */
         movl   %cr0, %eax
        andl    $(~((1 << 30) | (1 << 29))), %eax
        invd
@@ -86,31 +94,36 @@ clear_mtrrs:
        rep     stosl
 
        /* Enable Cache-as-RAM mode by disabling cache. */
-       disable_cache()
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
 
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE
        /* Enable cache for our code in Flash because we do XIP here */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
-       movl    $REAL_XIP_ROM_BASE, %eax
+       /*
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
+        * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+        */
+       movl    $copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 
        movl    $MTRRphysMask_MSR(1), %ecx
        xorl    %edx, %edx
-       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
 
-       enable_cache()
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $(~((1 << 30) | (1 << 29))), %eax
+       movl    %eax, %cr0
 
        /* Set up the stack pointer. */
-#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
+#if CONFIG_USBDEBUG
        /* Leave some space for the struct ehci_debug_info. */
        movl    $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
 #else
@@ -118,8 +131,8 @@ clear_mtrrs:
 #endif
        movl    %eax, %esp
 
-       restore_bist_result()
-
+       /* Restore the BIST result. */
+       movl    %ebp, %eax
        movl    %esp, %ebp
        pushl   %eax
 
@@ -132,11 +145,18 @@ clear_mtrrs:
 
        post_code(0x30)
 
-       disable_cache()
+       /* Disable cache. */
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
 
        post_code(0x31)
 
-       disable_mtrr()
+       /* Disable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       andl    $(~MTRRdefTypeEn), %eax
+       wrmsr
 
        post_code(0x31)
 
@@ -156,11 +176,17 @@ clear_mtrrs:
 
        post_code(0x33)
 
-       enable_cache()
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $~((1 << 30) | (1 << 29)), %eax
+       movl    %eax, %cr0
 
        post_code(0x36)
 
-       disable_cache()
+       /* Disable cache. */
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
 
        post_code(0x38)
 
@@ -170,18 +196,24 @@ clear_mtrrs:
        xorl    %edx, %edx
        wrmsr
        movl    $MTRRphysMask_MSR(0), %ecx
-       movl    $(~(1024 * 1024 - 1) | (1 << 11)), %eax
+       movl    $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
        xorl    %edx, %edx
        wrmsr
 
        post_code(0x39)
 
        /* And enable cache again after setting MTRRs. */
-       enable_cache()
+       movl    %cr0, %eax
+       andl    $~((1 << 30) | (1 << 29)), %eax
+       movl    %eax, %cr0
 
        post_code(0x3a)
 
-       enable_mtrr()
+       /* Enable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       orl     $MTRRdefTypeEn, %eax
+       wrmsr
 
        post_code(0x3b)
 
@@ -193,7 +225,7 @@ clear_mtrrs:
        /* Clear boot_complete flag. */
        xorl    %ebp, %ebp
 __main:
-       post_code(0x11)
+       post_code(POST_PREPARE_RAMSTAGE)
        cld                     /* Clear direction flag. */
 
        movl    %ebp, %esi
@@ -204,7 +236,7 @@ __main:
        call    copy_and_run
 
 .Lhlt:
-       post_code(0xee)
+       post_code(POST_DEAD_CODE)
        hlt
        jmp     .Lhlt