Remove XIP_ROM_BASE

[coreboot.git] / src / cpu / intel / car / cache_as_ram.inc

diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 2310d7d9d2cc1bc31ed2b0ce599ba5752ed763c9..7742a68225e7392a30e98cb80921e33f5180ddd3 100644 (file)
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -229,13 +229,7 @@ clear_fixed_var_mtrr_out:
        simplemask CacheSize, 0
        wrmsr
 
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
-
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
+#if CONFIG_XIP_ROM_SIZE
 
        /*
         * Enable write base caching so we can do execute in place (XIP)
@@ -244,11 +238,11 @@ clear_fixed_var_mtrr_out:
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
        /*
-        * IMPORTANT: The two lines below can _not_ be written like this:
-        *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
         * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
         */
-       movl    $REAL_XIP_ROM_BASE, %eax
+       movl    $copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 
@@ -256,7 +250,7 @@ clear_fixed_var_mtrr_out:
        movl    $0x0000000f, %edx
        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
 
        /* Enable cache. */
        movl    %cr0, %eax