We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / cpu / amd / sc520 / sc520.c

diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c
index 07991825cd7dfa52b8d115becefa9baf794ae744..059e4fd2ebb090351b7c46e3a9096235fc38ef53 100644 (file)
--- a/src/cpu/amd/sc520/sc520.c
+++ b/src/cpu/amd/sc520/sc520.c
@@ -4,6 +4,7 @@
 
 #include <console/console.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <stdint.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -15,24 +16,11 @@
 #include <delay.h>
 #include "chip.h"
 
-
-/* hack for now */
-static void sc520_udelay(int microseconds) {
-        volatile int x;
-        for(x = 0; x < 1000; x++) 
-                ;  
-}
-
-/* looks like we define this now */
-void
-udelay(unsigned microseconds) {
-        sc520_udelay(microseconds); 
-}
 /*
- * set up basic things ... 
- * PAR should NOT go here, as it might change with the mainboard. 
+ * set up basic things ...
+ * PAR should NOT go here, as it might change with the mainboard.
  */
-static void cpu_init(device_t dev) 
+static void cpu_init(device_t dev)
 {
   unsigned long *l = (unsigned long *) 0xfffef088;
   int i;
@@ -43,9 +31,9 @@ static void cpu_init(device_t dev)
 }
 
 
-/* Ollie says: make a northbridge/amd/sc520. Ron sez: 
- * there is no real northbridge, keep it here in cpu. 
- * Ron wins, he's writing the code. 
+/* Ollie says: make a northbridge/amd/sc520. Ron sez:
+ * there is no real northbridge, keep it here in cpu.
+ * Ron wins, he's writing the code.
  */
 static void sc520_enable_resources(struct device *dev) {
        unsigned char command;
@@ -76,7 +64,7 @@ static void sc520_read_resources(device_t dev)
        res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
        res = new_resource(dev, 3); /* IOAPIC */
-       res->base = 0xfec00000;
+       res->base = IO_APIC_ADDR;
        res->size = 0x00001000;
        res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
@@ -97,54 +85,13 @@ static const struct pci_driver cpu_driver __pci_driver = {
        .device = 0x3000
 };
 
-static void ram_resource(device_t dev, unsigned long index,
-        unsigned long basek, unsigned long sizek)
-{
-        struct resource *resource;
-       printk(BIOS_SPEW, "%s sizek 0x%lx\n", __func__, sizek);
-        if (!sizek) {
-                return;
-        }
-        resource = new_resource(dev, index);
-        resource->base  = ((resource_t)basek) << 10;
-        resource->size  = ((resource_t)sizek) << 10;
-        resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
-                IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
-
-static void tolm_test(void *gp, struct device *dev, struct resource *new)
-{
-       struct resource **best_p = gp;
-       struct resource *best;
-       best = *best_p;
-       if (!best || (best->base > new->base)) {
-               best = new;
-       }
-       *best_p = best;
-}
-
-static uint32_t find_pci_tolm(struct bus *bus)
-{
-       struct resource *min;
-       uint32_t tolm;
-  printk(BIOS_SPEW, "%s\n", __func__);
-       min = 0;
-       search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
-       tolm = 0xffffffffUL;
-       if (min && tolm > min->base) {
-               tolm = min->base;
-       }
-  printk(BIOS_SPEW, "%s returns 0x%x\n", __func__, tolm);
-       return tolm;
-}
-
 static void pci_domain_set_resources(device_t dev)
 {
        device_t mc_dev;
         uint32_t pci_tolm;
   printk(BIOS_SPEW, "%s\n", __func__);
-        pci_tolm = find_pci_tolm(&dev->link[0]);
-       mc_dev = dev->link[0].children;
+        pci_tolm = find_pci_tolm(dev->link_list);
+       mc_dev = dev->link_list->children;
        if (mc_dev) {
                unsigned long tomk, tolmk;
                //              unsigned char rambits;
@@ -154,16 +101,16 @@ static void pci_domain_set_resources(device_t dev)
                for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
                        unsigned char reg;
                        reg = pci_read_config8(mc_dev, ramregs[i]);
-                       /* these are ENDING addresses, not sizes. 
+                       /* these are ENDING addresses, not sizes.
                         * if there is memory in this slot, then reg will be > rambits.
-                        * So we just take the max, that gives us total. 
+                        * So we just take the max, that gives us total.
                         * We take the highest one to cover for once and future coreboot
                         * bugs. We warn about bugs.
                         */
                        if (reg > rambits)
                                rambits = reg;
                        if (reg < rambits)
-                               printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n", 
+                               printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
                                        ramregs[i]);
                }
                printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
@@ -181,7 +128,7 @@ static void pci_domain_set_resources(device_t dev)
                idx = 10;
                ram_resource(dev, idx++, 0, tolmk);
        }
-       assign_resources(&dev->link[0]);
+       assign_resources(dev->link_list);
 }
 
 #if 0
@@ -258,5 +205,5 @@ static void enable_dev(struct device *dev)
 
 struct chip_operations cpu_amd_sc520_ops = {
        CHIP_NAME("AMD Elan SC520 CPU")
-       .enable_dev = enable_dev, 
+       .enable_dev = enable_dev,
 };