Revert r5902 to make code more readable again. At least three people like to

[coreboot.git] / src / cpu / amd / model_gx2 / cpureginit.c

diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c
index f8efd9a2a57494160e34241df683c282fbaaa70c..0fc852d531f2ff7c05985e426789e321c1afc16b 100644 (file)
--- a/src/cpu/amd/model_gx2/cpureginit.c
+++ b/src/cpu/amd/model_gx2/cpureginit.c
@@ -4,8 +4,6 @@ void cpuRegInit (void)
 {
        int msrnum;
        msr_t msr;
-       /* Turn on BTM for early debug based on setup. */
-       // if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) {
        /* The following is only for diagnostics mode; do not use for OLPC */
        if (0) {
                /* Set Diagnostic Mode */
@@ -90,16 +88,13 @@ void cpuRegInit (void)
        msr.lo =  0x00000603C;
        wrmsr(msrnum, msr);
 
-/* Only do this if we are building for 5535 */
 /* FooGlue Setup */
-#if 1
-       /* Enable CIS mode B in FooGlue */
-       msrnum = MSR_FG + 0x10;
+       /* Set CS5535/CS5536 mode in FooGlue */
+       msrnum = FG_GIO_MSR_SEL;
        msr = rdmsr(msrnum);
        msr.lo &= ~3;
-       msr.lo |= 2;            /* ModeB */
+       msr.lo |= 2;            /* IIOC mode CS5535/CS5536 enable. (according to Jordan Crouse the databook is wrong bits 1:0 have to be 2 instead of 1) */
        wrmsr(msrnum, msr);
-#endif
 
 /* Disable DOT PLL. Graphics init will enable it if needed. */
        msrnum = GLCP_DOTPLL;
@@ -125,37 +120,10 @@ void cpuRegInit (void)
        }
 
 /* FPU impercise exceptions bit */
-       //if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {
        {
                msrnum = CPU_FPU_MSR_MODE;
                msr = rdmsr(msrnum);
                msr.lo |= FPU_IE_SET;
                wrmsr(msrnum, msr);
        }
-
-#if 0
-       /* Cache Overides */
-       /* This code disables the data cache.  Don't execute this
-        * unless you're testing something.
-        */
-       /* Allow NVRam to override DM Setup */
-       //if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {
-       {
-               msrnum = CPU_DM_CONFIG0;
-               msr = rdmsr(msrnum);
-               msr.lo |=  DM_CONFIG0_LOWER_DCDIS_SET;
-               wrmsr(msrnum, msr);
-       }
-       /* This code disables the instruction cache.  Don't execute
-        * this unless you're testing something.
-       */
-       /* Allow NVRam to override IM Setup */
-       //if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {
-       {
-               msrnum = CPU_IM_CONFIG;
-               msr = rdmsr(msrnum);
-               msr.lo |=  IM_CONFIG_LOWER_ICD_SET;
-               wrmsr(msrnum, msr);
-       }
-#endif
 }