Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9

[coreboot.git] / src / cpu / amd / car / cache_as_ram.inc

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 5a19a0c0b0f9cc3a3dfd493c9c4bd3cd7c4f620a..b9e02f3b8fdd30e34e324a41e0031146d06b6549 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -18,7 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <cpu/x86/car.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 
@@ -46,7 +45,8 @@
  *   xmm3: Backup EBX
  */
 
-       save_bist_result()
+       /* Save the BIST result. */
+       movl    %eax, %ebp
 
        /*
         * For normal part %ebx already contain cpu_init_detected
@@ -56,7 +56,10 @@
 cache_as_ram_setup:
        post_code(0xa0)
 
-       enable_sse()
+       /* Enable SSE. */
+       movl    %cr4, %eax
+       orl     $(3 << 9), %eax
+       movl    %eax, %cr4
 
        /* Figure out the CPU family. */
        cvtsi2sd %ebx, %xmm3
@@ -74,7 +77,7 @@ cache_as_ram_setup:
        /* Check if cpu_init_detected. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       andl    $(1 << 11), %eax
+       andl    $MTRRdefTypeEn, %eax
        movl    %eax, %ebx      /* We store the status. */
 
        jmp_if_k8(CAR_FAM10_out_post_errata)
@@ -132,14 +135,34 @@ CAR_FAM10_out:
        wrmsr
 
 #if CONFIG_MMCONF_SUPPORT
-       /* Set MMIO config space BAR. */
-       movl    $MSR_MCFG_BASE, %ecx
-       rdmsr
-       andl    $(~(0xfff00000 | (0xf << 2))), %eax
-       orl     $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000)), %eax
-       orl     $((8 << 2) | (1 << 0)), %eax
-       andl    $(~(0x0000ffff)), %edx
-       orl     $(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx
+   #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)
+   #error "MMCONF_BASE_ADDRESS too big"
+   #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)
+   #error "MMCONF_BASE_ADDRESS not 1MB aligned"
+   #endif
+       movl    $0, %edx
+       movl    $((CONFIG_MMCONF_BASE_ADDRESS) | (1 << 0)), %eax
+   #if (CONFIG_MMCONF_BUS_NUMBER == 1)
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 2)
+       orl     $(1 << 2), %eax
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 4)
+       orl     $(2 << 2), %eax 
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 8)
+       orl     $(3 << 2), %eax
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 16)
+       orl     $(4 << 2), %eax
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 32)
+       orl     $(5 << 2), %eax
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 64)
+       orl     $(6 << 2), %eax
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 128)
+       orl     $(7 << 2), %eax
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 256)
+       orl     $(8 << 2), %eax
+   #else
+       #error "bad MMCONF_BUS_NUMBER value"
+   #endif
+       movl    $(0xc0010058), %ecx
        wrmsr
 #endif
 
@@ -258,23 +281,17 @@ clear_fixed_var_mtrr_out:
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
-
        /* Enable write base caching so we can do execute in place (XIP)
         * on the flash ROM.
         */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
        /*
-        * IMPORTANT: The two lines below can _not_ be written like this:
-        *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
         * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
         */
-       movl    $REAL_XIP_ROM_BASE, %eax
+       movl    $copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 
@@ -283,7 +300,7 @@ clear_fixed_var_mtrr_out:
        jmp_if_k8(wbcache_post_fam10_setup)
        movl    $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
 wbcache_post_fam10_setup:
-       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
@@ -301,7 +318,10 @@ wbcache_post_fam10_setup:
 
        post_code(0xa1)
 
-       enable_cache()
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $(~((1 << 30) | (1 << 29))), %eax
+       movl    %eax, %cr0
 
        jmp_if_k8(fam10_end_part1)
 
@@ -383,9 +403,13 @@ CAR_FAM10_ap_out:
 
        post_code(0xa5)
 
-       disable_sse()
+       /* Disable SSE. */
+       movl    %cr4, %eax
+       andl    $~(3 << 9), %eax
+       movl    %eax, %cr4
 
-       restore_bist_result()
+       /* Restore the BIST result. */
+       movl    %ebp, %eax
 
        /* We need to set EBP? No need. */
        movl    %esp, %ebp