Remove XIP_ROM_BASE

[coreboot.git] / src / cpu / amd / car / cache_as_ram.inc

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 26cdec3fbe69c1f1951e549aa3dd0c39bff04fc7..955aec95146ac0a22feb76594e10281945f5baae 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -77,7 +77,7 @@ cache_as_ram_setup:
        /* Check if cpu_init_detected. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       andl    $(1 << 11), %eax
+       andl    $MTRRdefTypeEn, %eax
        movl    %eax, %ebx      /* We store the status. */
 
        jmp_if_k8(CAR_FAM10_out_post_errata)
@@ -279,13 +279,7 @@ clear_fixed_var_mtrr_out:
        movl    $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
        wrmsr
 
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
-
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
+#if CONFIG_XIP_ROM_SIZE
 
        /* Enable write base caching so we can do execute in place (XIP)
         * on the flash ROM.
@@ -293,12 +287,12 @@ clear_fixed_var_mtrr_out:
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
        /*
-        * IMPORTANT: The two lines below can _not_ be written like this:
-        *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
         * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
         */
-       movl    $REAL_XIP_ROM_BASE, %eax
-       orl     $MTRR_TYPE_WRPROT, %eax
+       movl    $copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+       orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 
        movl    $MTRRphysMask_MSR(1), %ecx
@@ -306,9 +300,9 @@ clear_fixed_var_mtrr_out:
        jmp_if_k8(wbcache_post_fam10_setup)
        movl    $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
 wbcache_post_fam10_setup:
-       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
 
        /* Set the default memory type and enable fixed and variable MTRRs. */
        movl    $MTRRdefType_MSR, %ecx